diff --git a/docs/conceptual/l2-cache.rst b/docs/conceptual/l2-cache.rst index 069d80d63..805e9999d 100644 --- a/docs/conceptual/l2-cache.rst +++ b/docs/conceptual/l2-cache.rst @@ -19,7 +19,7 @@ interleaving) which can largely operate independently. Mapping of incoming requests to a specific L2 channel is determined by a hashing mechanism that attempts to evenly distribute requests across the L2 channels. Requests that miss in the L2 cache are passed out to :ref:`Infinity Fabric™ ` to -be routed to the appropriate memory location. See :cdna3-white-paper:`<9>` for +be routed to the appropriate memory location. See :cdna3-white-paper:`9` for more information. The L2 cache metrics reported by ROCm Compute Profiler are broken down into four diff --git a/docs/conceptual/performance-model.rst b/docs/conceptual/performance-model.rst index 41cbb217f..cb98f8cab 100644 --- a/docs/conceptual/performance-model.rst +++ b/docs/conceptual/performance-model.rst @@ -34,6 +34,19 @@ to use ROCm Compute Profiler to optimize your code. For a comparison of AMD Instinct accelerator specifications, refer to :doc:`Hardware specifications `. +Supported features +================== + +.. list-table:: + :header-rows: 1 + + * - Feature + - Support + + * - Infinity Cache + - Support + + In this chapter, the AMD Instinct performance model used by ROCm Compute Profiler is divided into a handful of key hardware blocks, each detailed in the following sections: