From 352eee9d9bc5c901a7319e5a6f1b68917363c349 Mon Sep 17 00:00:00 2001 From: DMG Karthik <146181807+karthdmg-xilinx@users.noreply.github.com> Date: Tue, 28 Jan 2025 08:53:01 +0530 Subject: [PATCH] resetting aws clocking module using AWS API (#8719) Signed-off-by: karthik dmg --- .../driver/linux/xocl/userpf/xocl_ioctl.c | 37 +++---------------- .../pcie/tools/cloud-daemon/aws/aws_dev.cpp | 30 +++++++++++++++ .../pcie/tools/cloud-daemon/aws/aws_dev.h | 2 + 3 files changed, 38 insertions(+), 31 deletions(-) diff --git a/src/runtime_src/core/pcie/driver/linux/xocl/userpf/xocl_ioctl.c b/src/runtime_src/core/pcie/driver/linux/xocl/userpf/xocl_ioctl.c index fe2c918b62e..cb3f965ced9 100644 --- a/src/runtime_src/core/pcie/driver/linux/xocl/userpf/xocl_ioctl.c +++ b/src/runtime_src/core/pcie/driver/linux/xocl/userpf/xocl_ioctl.c @@ -539,32 +539,6 @@ xocl_resolver(struct xocl_dev *xdev, struct axlf *axlf, xuid_t *xclbin_id, return ret; } -/* This is a Workaround function for AWS F2 to reset the clock registers. - * This function also incurs a delay of 10seconds to work around AWS ocl timeout issue. - * These changes will be removed once the issue is addressed in AWS F2 instance. - */ -void aws_reset_clock_registers(xdev_handle_t xdev) -{ - struct xocl_dev_core *core = XDEV(xdev); - resource_size_t bar0_clk1, bar0_clk2; - void __iomem *vbar0_clk1, *vbar0_clk2; - - userpf_info(xdev, "AWS F2 WA, waiting to reset clock registers after Load "); - msleep(10000); - - bar0_clk1 = pci_resource_start(core->pdev, 0) + 0x4058014; - bar0_clk2 = pci_resource_start(core->pdev, 0) + 0x4058010; - vbar0_clk1 = ioremap_nocache(bar0_clk1, 32); - vbar0_clk2 = ioremap_nocache(bar0_clk2, 32); - - iowrite32(0, vbar0_clk1); - iowrite32(0, vbar0_clk2); - - iounmap(vbar0_clk1); - iounmap(vbar0_clk2); - return; -} - int xocl_read_axlf_helper(struct xocl_drm *drm_p, struct drm_xocl_axlf *axlf_ptr, uint32_t qos, uint32_t *slot) @@ -796,11 +770,12 @@ xocl_read_axlf_helper(struct xocl_drm *drm_p, struct drm_xocl_axlf *axlf_ptr, } else { userpf_info(xdev, "Loaded xclbin %pUb", &bin_obj.m_header.uuid); - /* Work around added for AWS F2 Instance to perform delay and reset clock registers */ - if(core->pdev->device == 0xf010) - { - aws_reset_clock_registers(xdev); - } + /* Work around added for AWS F2 Instance to perform delay */ + if(core->pdev->device == 0xf010) + { + userpf_info(xdev, "AWS F2 WA, waiting after AFI Load "); + msleep(10000); + } } out_done: diff --git a/src/runtime_src/core/pcie/tools/cloud-daemon/aws/aws_dev.cpp b/src/runtime_src/core/pcie/tools/cloud-daemon/aws/aws_dev.cpp index f5a3943aaf2..7046002ad57 100644 --- a/src/runtime_src/core/pcie/tools/cloud-daemon/aws/aws_dev.cpp +++ b/src/runtime_src/core/pcie/tools/cloud-daemon/aws/aws_dev.cpp @@ -533,6 +533,26 @@ int AwsDev::awsLoadXclBin(const xclBin *buffer) opt.afi_id = afi_id; opt.slot_id = mBoardNumber; retVal = fpga_mgmt_load_local_image_with_options(&opt); + + if(imageInfoOld.spec.map[FPGA_APP_PF].device_id == 0xf010) + { + const clock_freq_topology* clockSection = get_clock_freq_from_axlf(axlfbuffer); + uint32_t clock_mains[4]; + + if(clockSection) { + for(int32_t i = 0; i < clockSection->m_count; i++) { + const struct clock_freq* clk = &(clockSection->m_clock_freq[i]); + clock_mains[i] = clk->m_freq_Mhz; + } + } + + syslog(LOG_ERR, "WA to skip id=%x", imageInfoOld.spec.map[FPGA_APP_PF].device_id); + aws_clkgen_set_dynamic(mBoardNumber, 125 /*default */, clock_mains[2]/*clk_extra_b0*/, + clock_mains[3]/*clk_extra_c0*/, clock_mains[1]/*hbm*/, 0); + + return 0; + } + if (retVal == FPGA_ERR_DRAM_DATA_RETENTION_NOT_POSSIBLE || retVal == FPGA_ERR_DRAM_DATA_RETENTION_FAILED || retVal == FPGA_ERR_DRAM_DATA_RETENTION_SETUP_FAILED) { @@ -778,4 +798,14 @@ char *AwsDev::get_afi_from_axlf(const axlf *buffer) return nullptr; return afid; } + +const clock_freq_topology* AwsDev::get_clock_freq_from_axlf(const axlf *buffer) +{ + const axlf_section_header *clk_header = xclbin::get_axlf_section(buffer, CLOCK_FREQ_TOPOLOGY); + char *clk_topo = const_cast(reinterpret_cast(buffer)); + clk_topo += clk_header->m_sectionOffset; + + return (reinterpret_cast(clk_topo)); +} + #endif diff --git a/src/runtime_src/core/pcie/tools/cloud-daemon/aws/aws_dev.h b/src/runtime_src/core/pcie/tools/cloud-daemon/aws/aws_dev.h index 7ee7a93fc62..5dd7a81e448 100644 --- a/src/runtime_src/core/pcie/tools/cloud-daemon/aws/aws_dev.h +++ b/src/runtime_src/core/pcie/tools/cloud-daemon/aws/aws_dev.h @@ -27,6 +27,7 @@ #ifndef INTERNAL_TESTING_FOR_AWS #include "fpga_pci.h" #include "fpga_mgmt.h" +#include "fpga_clkgen.h" #include "hal/fpga_common.h" #endif @@ -115,6 +116,7 @@ class AwsDev #else int sleepUntilLoaded( const std::string &afi, fpga_mgmt_image_info* new_afi ); char* get_afi_from_axlf(const axlf * buffer); + const clock_freq_topology* get_clock_freq_from_axlf(const axlf *buffer); int index; #endif };