Dataflow build taking too long

[Adityasrinivas24]

Hi,
I customised CNV(w8a8) for weight and activation bit width of 8 and tried building stiched ips, bitstream and pynq driver as shown here. But the step_hw_ipgen generation step is taking unbelievably long to finish and I'm aware that step_set_fifo_depths takes longer.

What parameters i should consider tuning for a faster build? Once a benchmark has been set, I plan on fine tuning for better performance

[fpjentzsch]

Hi,
8 bit precision is a lot for the FINN back-end and might produce a very large and time consuming design. Maybe you can start from lower bit widths and only increase them in layers where it is absolutely necessary?

In general, setting the mem_mode of your layers (e.g. MVAU) to internal_decoupled should result in faster HLS than internal_embedded (const). Switching to the new RTL components introduced in the latest FINN release might also reduce build time significantly because no HLS has to take place.