Issue with 'finn_design' Module Not Found During Synthesis in Vivado

[Nishith0402]

Hi,

I am currently working on a project involving a FINN IP module, which was generated through the FINN compiler and included in a new Vivado project. The project block design includes the following components: ZYNQ7 PS, AXI DMA, AXI4 STREAM DATA FIFO, AXI stream data width converter, and the FINN IP module.

I have encountered a synthesis error indicating that the 'finn_design' module is not found. The error is reported in the design_1_finn_design_0_0.v file, even though the finn_design.v file is already uploaded into the project sources directory in Vivado(Red rectangular box) . I have included repositories of FINN IP and its sub-modules as well.

Below are the relevant screenshots for reference:

Block Design:

Synthesis Error:

Project Hierarchy:

Could you please provide guidance on resolving this issue? Any help would be greatly appreciated.

Thank you!

[auphelia]

Hi @Nishith0402 ,
This tutorial might be helpful: https://github.com/Xilinx/finn/tree/dev/tutorials/fpga_flow
From your description I cannot tell, but we sometimes also see issues when moving the FINN IP to a different location/server for integration into a bigger design. Because there will be some internal paths set, e.g. to the weight files and these paths break when the design is moved.