cptra_ss_clk_i frequency requirement

[steven-bellock]

What does (emphasis mine)

iii. If a different frequency is required, ensure that a clock divider or PLL is used to generate the 200 MHz clock before connection.

mean? It sounds like the Integrator can alter the frequency, but then it says it needs to be 200 MHz, which is already stated in the first bullet

i. Verify that the SoC or system-level clock source provides a stable 200 MHz clock.

If the clock frequency has to be 200 MHz then remove the third bullet. In addition, quantify what "stable" means and specify a tolerance for the frequency, for example 200 MHz ± 1 MHz.