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AMDGPU silently converts incorrect physical register asm constraint to virtual register #123208

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arsenm opened this issue Jan 16, 2025 · 2 comments · Fixed by #123590
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AMDGPU silently converts incorrect physical register asm constraint to virtual register #123208

arsenm opened this issue Jan 16, 2025 · 2 comments · Fixed by #123590
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accepts-invalid backend:AMDGPU

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@arsenm
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arsenm commented Jan 16, 2025 

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx940 < %s

define void @invalid_sgpr(<2 x i32> inreg %arg0) {
  call void asm sideeffect "; use $0", "{s[1:2]}"(<2 x i32> %arg0)
  ret void
}

s[1:2] is not a valid SGPR reference as 64-bit SGPRs require even alignment. This is silently accepted, and appears to be treated as a virtual register constraint. In -stop-after=finalize-isel, I see:

    %10:sreg_64 = COPY %11
    INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3997705 /* reguse:SReg_64 */, %10
@llvmbot
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llvmbot commented Jan 16, 2025

@llvm/issue-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

``` ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx940 < %s

define void @invalid_sgpr(<2 x i32> inreg %arg0) {
call void asm sideeffect "; use $0", "{s[1:2]}"(<2 x i32> %arg0)
ret void
}


s[1:2] is not a valid SGPR reference as 64-bit SGPRs require even alignment. This is silently accepted, and appears to be treated as a virtual register constraint. In -stop-after=finalize-isel, I see:


%10:sreg_64 = COPY %11
INLINEASM &amp;"; use $0", 1 /* sideeffect attdialect */, 3997705 /* reguse:SReg_64 */, %10

</details>

@ritter-x2a ritter-x2a self-assigned this Jan 20, 2025
ritter-x2a added a commit to ritter-x2a/llvm-project that referenced this issue Jan 20, 2025
@ritter-x2a
[AMDGPU] Reject misaligned SGPR constraints for inline asm
9b8bee2 
The indices of SGPR register pairs need to be 2-aligned and SGPR
quadruplets need to be 4-aligned. With this patch, we report an error
when inline asm register constraints specify a misaligned register
index, instead of silently dropping the specified index.

Fixes llvm#123208
@ritter-x2a ritter-x2a mentioned this issue Jan 20, 2025
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#123590 has a patch for this problem.

ritter-x2a added a commit that referenced this issue Jan 20, 2025
@ritter-x2a @arsenm
[AMDGPU] Reject misaligned SGPR constraints for inline asm (#123590)
cc5eba1 
The indices of SGPR register pairs need to be 2-aligned and SGPR
quadruplets need to be 4-aligned. With this patch, we report an error
when inline asm register constraints specify a misaligned register
index, instead of silently dropping the specified index.

Fixes #123208

---------

Co-authored-by: Matt Arsenault <[email protected]>
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[AMDGPU] Reject misaligned SGPR constraints for inline asm ritter-x2a/llvm-project
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