From ab8ca02e105578b425b2a15f5e357351e822a813 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Str=C3=B6mbergson?= Date: Mon, 18 Mar 2024 14:41:52 +0100 Subject: [PATCH] Implement cs0 and cs1 as logic equations, not muxes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Joachim Strömbergson --- hw/application_fpga/rtl/ram.v | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/application_fpga/rtl/ram.v b/hw/application_fpga/rtl/ram.v index df9728ce..bb91f7f1 100644 --- a/hw/application_fpga/rtl/ram.v +++ b/hw/application_fpga/rtl/ram.v @@ -125,14 +125,12 @@ module ram( //---------------------------------------------------------------- always @* begin : mem_mux - cs0 = 1'h0; - cs1 = 1'h0; + cs0 = ~address[14] & cs; + cs1 = address[14] & cs; if (address[14]) begin - cs1 = cs; muxed_read_data = read_data1; end else begin - cs0 = cs; muxed_read_data = read_data0; end end