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Modify MSUB, NMADD, NMSUB behaviour to differs from other instruction…
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…s. (openhwgroup#2712)

MSUB = rs1 - rs2 - rs3
NMADD = ~(rs1 + rs2 + rs3)
NMSUB = ~(rs1 - rs2 - rs3)
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@Gchauvon
Gchauvon authored Jan 17, 2025
1 parent e840a61 commit 3d2ff00
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Showing 4 changed files with 47 additions and 20 deletions.
28 changes: 26 additions & 2 deletions core/cvxif_example/copro_alu.sv
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Expand Up @@ -88,8 +88,32 @@ module copro_alu
rd_n = rd_i;
we_n = 1'b1;
end
cvxif_instr_pkg::ADD_RS3_R4: begin
result_n = NrRgprPorts == 3 ? registers_i[2] + registers_i[1] + registers_i[0] : registers_i[1] + registers_i[0];
cvxif_instr_pkg::MADD_RS3_R4: begin
result_n = NrRgprPorts == 3 ? (registers_i[0] + registers_i[1] + registers_i[2]) : (registers_i[0] + registers_i[1]);
hartid_n = hartid_i;
id_n = id_i;
valid_n = 1'b1;
rd_n = rd_i;
we_n = 1'b1;
end
cvxif_instr_pkg::MSUB_RS3_R4: begin
result_n = NrRgprPorts == 3 ? (registers_i[0] - registers_i[1] - registers_i[2]) : (registers_i[0] - registers_i[1]);
hartid_n = hartid_i;
id_n = id_i;
valid_n = 1'b1;
rd_n = rd_i;
we_n = 1'b1;
end
cvxif_instr_pkg::NMADD_RS3_R4: begin
result_n = NrRgprPorts == 3 ? ~(registers_i[0] + registers_i[1] + registers_i[2]) : ~(registers_i[0] + registers_i[1]);
hartid_n = hartid_i;
id_n = id_i;
valid_n = 1'b1;
rd_n = rd_i;
we_n = 1'b1;
end
cvxif_instr_pkg::NMSUB_RS3_R4: begin
result_n = NrRgprPorts == 3 ? ~(registers_i[0] - registers_i[1] - registers_i[2]) : ~(registers_i[0] - registers_i[1]);
hartid_n = hartid_i;
id_n = id_i;
valid_n = 1'b1;
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15 changes: 9 additions & 6 deletions core/cvxif_example/include/cvxif_instr_pkg.sv
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Expand Up @@ -18,8 +18,11 @@ package cvxif_instr_pkg;
DOUBLE_RS1 = 4'b0011,
DOUBLE_RS2 = 4'b0100,
ADD_MULTI = 4'b0101,
ADD_RS3_R4 = 4'b0110,
ADD_RS3_R = 4'b0111
MADD_RS3_R4 = 4'b0110,
MSUB_RS3_R4 = 4'b0111,
NMADD_RS3_R4 = 4'b1000,
NMSUB_RS3_R4 = 4'b1001,
ADD_RS3_R = 4'b1111
} opcode_t;


Expand Down Expand Up @@ -105,31 +108,31 @@ package cvxif_instr_pkg;
32'b00000_00_00000_00000_0_00_00000_1000011, // MADD opcode
mask: 32'b00000_11_00000_00000_1_11_00000_1111111,
resp : '{accept : 1'b1, writeback : 1'b1, register_read : {1'b1, 1'b1, 1'b1}},
opcode : ADD_RS3_R4
opcode : MADD_RS3_R4
},
'{
// Custom Add Multi rs1 : cus_add rd, rs1, rs1
instr:
32'b00000_00_00000_00000_0_00_00000_1000111, // MSUB opcode
mask: 32'b00000_11_00000_00000_1_11_00000_1111111,
resp : '{accept : 1'b1, writeback : 1'b1, register_read : {1'b1, 1'b1, 1'b1}},
opcode : ADD_RS3_R4
opcode : MSUB_RS3_R4
},
'{
// Custom Add Multi rs1 : cus_add rd, rs1, rs1
instr:
32'b00000_00_00000_00000_0_00_00000_1001011, // NMSUB opcode
mask: 32'b00000_11_00000_00000_1_11_00000_1111111,
resp : '{accept : 1'b1, writeback : 1'b1, register_read : {1'b1, 1'b1, 1'b1}},
opcode : ADD_RS3_R4
opcode : NMSUB_RS3_R4
},
'{
// Custom Add Multi rs1 : cus_add rd, rs1, rs1
instr:
32'b00000_00_00000_00000_0_00_00000_1001111, // NMADD opcode
mask: 32'b00000_11_00000_00000_1_11_00000_1111111,
resp : '{accept : 1'b1, writeback : 1'b1, register_read : {1'b1, 1'b1, 1'b1}},
opcode : ADD_RS3_R4
opcode : NMADD_RS3_R4
}
};

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12 changes: 6 additions & 6 deletions verif/env/uvme/cvxif_vseq/custom_instructions_cvxif_1_0_0.rst
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Expand Up @@ -70,25 +70,25 @@ Except for 4 of them using opcode `MADD, MSUB, NMADD, NMSUB`

**Format**: addi rd, rs1, rs2, rs3 -> |rs3|00|rs2|rs1|000|rd|100_0111|

**Description**: add register rs1, rs2 to rs3, and store the result in rd.
**Description**: subtract register rs2 and rs3 from rs1 and store the result in rd.

**Pseudocode**: x[rd] = x[rs1] + x[rs2] + x[rs3]
**Pseudocode**: x[rd] = x[rs1] - x[rs2] - x[rs3]

- **CUS_ADD_RS3_NMADD**: Custom Add with RS3 opcode == NMADD

**Format**: addi rd, rs1, rs2, rs3 -> |rs3|00|rs2|rs1|000|rd|100_1111|

**Description**: add register rs1, rs2 to rs3, and store the result in rd.
**Description**: add register rs1, rs2 to rs3, negate the sum, and store the result in rd.

**Pseudocode**: x[rd] = x[rs1] + x[rs2] + x[rs3]
**Pseudocode**: x[rd] = ¬(x[rs1] + x[rs2] + x[rs3])

- **CUS_ADD_RS3_NMSUB**: Custom Add with RS3 opcode == NMSUB

**Format**: addi rd, rs1, rs2, rs3 -> |rs3|00|rs2|rs1|000|rd|100_1011|

**Description**: add register rs1, rs2 to rs3, and store the result in rd.
**Description**: subtract register rs2 and rs3 from rs1, negate the difference, and store the result in rd.

**Pseudocode**: x[rd] = x[rs1] + x[rs2] + x[rs3]
**Pseudocode**: x[rd] = ¬(x[rs1] - x[rs2] - x[rs3])

- **CUS_ADD_RS3_RTYPE**: Custom Add with RS3, rd is x10 (a0)

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12 changes: 6 additions & 6 deletions verif/env/uvme/cvxif_vseq/uvme_cvxif_vseq.sv
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Expand Up @@ -378,31 +378,31 @@ task uvme_cvxif_vseq_c::do_instr_result();
end
"CUS_ADD_RS3_MSUB": begin
if (req_item.register.rs_valid == 3'b111) begin
resp_item.result.data = req_item.register.rs[0] + req_item.register.rs[1] + req_item.register.rs[2];
resp_item.result.data = req_item.register.rs[0] - req_item.register.rs[1] - req_item.register.rs[2];
resp_item.result.rd = req_item.issue_req.instr[11:7];
end
else if (req_item.register.rs_valid == 2'b11) begin
resp_item.result.data = req_item.register.rs[0] + req_item.register.rs[1];
resp_item.result.data = req_item.register.rs[0] - req_item.register.rs[1];
resp_item.result.rd = req_item.issue_req.instr[11:7];
end
end
"CUS_ADD_RS3_NMADD": begin
if (req_item.register.rs_valid == 3'b111) begin
resp_item.result.data = req_item.register.rs[0] + req_item.register.rs[1] + req_item.register.rs[2];
resp_item.result.data = ~(req_item.register.rs[0] + req_item.register.rs[1] + req_item.register.rs[2]);
resp_item.result.rd = req_item.issue_req.instr[11:7];
end
else if (req_item.register.rs_valid == 2'b11) begin
resp_item.result.data = req_item.register.rs[0] + req_item.register.rs[1];
resp_item.result.data = ~(req_item.register.rs[0] + req_item.register.rs[1]);
resp_item.result.rd = req_item.issue_req.instr[11:7];
end
end
"CUS_ADD_RS3_NMSUB": begin
if (req_item.register.rs_valid == 3'b111) begin
resp_item.result.data = req_item.register.rs[0] + req_item.register.rs[1] + req_item.register.rs[2];
resp_item.result.data = ~(req_item.register.rs[0] - req_item.register.rs[1] - req_item.register.rs[2]);
resp_item.result.rd = req_item.issue_req.instr[11:7];
end
else if (req_item.register.rs_valid == 2'b11) begin
resp_item.result.data = req_item.register.rs[0] + req_item.register.rs[1];
resp_item.result.data = ~(req_item.register.rs[0] - req_item.register.rs[1]);
resp_item.result.rd = req_item.issue_req.instr[11:7];
end
end
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