modifications

10x-Engineers · Jan 16, 2025 · bbb10ee · bbb10ee
1 parent bdcebe8
commit bbb10ee
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Showing 7 changed files with 10 additions and 24 deletions.
diff --git a/core/compressed_decoder.sv b/core/compressed_decoder.sv
@@ -870,20 +870,13 @@ module compressed_decoder #(
                 3'b000,
                 riscv::OpcodeStoreFp
               };
-            end else if (CVA6Cfg.RVZCMP || CVA6Cfg.RVZCMT) begin
-              if (instr_i[12:10] == 3'b110 || instr_i[12:10] == 3'b111 || instr_i[12:10] == 3'b011) begin //is a push/pop instruction
-                is_macro_instr_o = 1;
-                instr_o = instr_i;
-              end else if (CVA6Cfg.RVZCMT && (instr_i[12:10] == 3'b000)) begin  //jt/jalt instruction
-                is_zcmt_instr_o = 1'b1;
-              end else begin
-                illegal_instr_o = 1'b1;
-              end
-            end else begin
-              illegal_instr_o = 1'b1;
-            end
+            end else if (CVA6Cfg.RVZCMP && (instr_i[12:10] == 3'b110 || instr_i[12:10] == 3'b111 || instr_i[12:10] == 3'b011)) begin
+              is_macro_instr_o = 1;
+              instr_o = instr_i;
+            end else if (CVA6Cfg.RVZCMT && (instr_i[12:10] == 3'b000))  //jt/jalt instruction
+              is_zcmt_instr_o = 1'b1;
+            else illegal_instr_o = 1'b1;
           end
-
           riscv::OpcodeC2Swsp: begin
             // c.swsp -> sw rs2, imm(x2)
             instr_o = {

diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv
@@ -298,7 +298,7 @@ module csr_regfile
   assign pmpaddr_o = pmpaddr_q[(CVA6Cfg.NrPMPEntries>0?CVA6Cfg.NrPMPEntries-1 : 0):0];
 
   riscv::fcsr_t fcsr_q, fcsr_d;
-  riscv::jvt_t jvt_q, jvt_d;
+  jvt_t jvt_q, jvt_d;
   // ----------------
   // Assignments
   // ----------------

diff --git a/core/cva6_rvfi.sv b/core/cva6_rvfi.sv
@@ -344,7 +344,6 @@ module cva6_rvfi
   `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, fflags, csr.fcsr_q.fflags)
   `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, frm, csr.fcsr_q.frm)
   `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, fcsr, { csr.fcsr_q.frm `COMMA csr.fcsr_q.fflags})
-  `CONNECT_RVFI_FULL(CVA6Cfg.RVZCMT, jvt, { csr.jvt_q.base `COMMA csr.jvt_q.mode})
 
   `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, ftran, csr.fcsr_q.fprec)
   `CONNECT_RVFI_SAME(CVA6Cfg.FpPresent, dcsr)

diff --git a/core/include/riscv_pkg.sv b/core/include/riscv_pkg.sv
@@ -863,12 +863,6 @@ package riscv;
     priv_lvl_t    prv;
   } dcsr_t;
 
-  //jvt struct
-  parameter JVT_ADDR_WIDTH = XLEN - 6;
-  typedef struct packed {
-    logic [JVT_ADDR_WIDTH-1:0] base;
-    logic [5:0] mode;
-  } jvt_t;
   // Instruction Generation *incomplete*
   function automatic logic [31:0] jal(logic [4:0] rd, logic [20:0] imm);
     // OpCode Jal

diff --git a/core/include/rvfi_types.svh b/core/include/rvfi_types.svh
@@ -131,7 +131,7 @@
 `define RVFI_PROBES_CSR_T(Cfg) struct packed { \
   riscv::fcsr_t fcsr_q; \
   riscv::dcsr_t dcsr_q; \
-  riscv::jvt_t jvt_q; \
+  logic [Cfg.XLEN-1:0] jvt_q; \
   logic [Cfg.XLEN-1:0] dpc_q; \
   logic [Cfg.XLEN-1:0] dscratch0_q; \
   logic [Cfg.XLEN-1:0] dscratch1_q; \

diff --git a/core/zcmt_decoder.sv b/core/zcmt_decoder.sv
@@ -77,7 +77,7 @@ module zcmt_decoder #(
           if (CVA6Cfg.XLEN == 32) begin  //It is only target for 32 bit targets in cva6 with No MMU
             table_address = {jvt_i.base, 6'b000000} + {24'h0, instr_i[7:2], 2'b00};
             req_port_o.address_index = table_address[9:0];
-            req_port_o.address_tag = table_address[CVA6Cfg.VLEN-1:10]; // No MMU support
+            req_port_o.address_tag = table_address[CVA6Cfg.VLEN-1:10];  // No MMU support
             state_d = TABLE_JUMP;
             req_port_o.data_req = 1'b1;
           end else illegal_instr_o = 1'b1;

diff --git a/verif/sim/cva6.py b/verif/sim/cva6.py
@@ -1035,7 +1035,7 @@ def check_verilator_version():
 
 def check_tools_version():
   check_cc_version()
-  check_spike_version()
+#  check_spike_version()
   check_verilator_version()