Add MCOMMIT instruction

Maratyszcza · Jan 7, 2024 · 8fae665 · 8fae665
1 parent ba35b62
commit 8fae665
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Showing 6 changed files with 26 additions and 0 deletions.
diff --git a/opcodes/x86.py b/opcodes/x86.py
@@ -467,6 +467,7 @@ class ISAExtension:
         - "CLWB"             := The `CLWB` instruction.
         - "CLZERO"           := The `CLZERO` instruction.
         - "CLDEMOTE"         := The `CLDEMOTE` instruction.
+        - "MCOMMIT"          := The `MCOMMIT` instruction.
         - "PREFETCH"         := The `PREFETCH` instruction (3dnow! Prefetch).
         - "PREFETCHW"        := The `PREFETCHW` instruction (3dnow! Prefetch/Intel PRFCHW).
         - "PREFETCHWT1"      := The `PREFETCHWT1` instruction.

diff --git a/opcodes/x86.xml b/opcodes/x86.xml
@@ -7166,6 +7166,17 @@
       </Encoding>
     </InstructionForm>
   </Instruction>
+  <Instruction name="MCOMMIT" summary="Memory COMMIT">
+    <InstructionForm gas-name="mcommit">
+      <ISA id="MCOMMIT"/>
+      <Encoding>
+        <Prefix byte="F3" mandatory="true"/>
+        <Opcode byte="0F"/>
+        <Opcode byte="01"/>
+        <Opcode byte="FA"/>
+      </Encoding>
+    </InstructionForm>
+  </Instruction>
   <Instruction name="MFENCE" summary="Memory Fence">
     <InstructionForm gas-name="mfence" go-name="MFENCE">
       <ISA id="SSE2"/>

diff --git a/opcodes/x86.xsd b/opcodes/x86.xsd
@@ -400,6 +400,7 @@
 			<xs:enumeration value="CLWB" />
 			<xs:enumeration value="CLZERO" />
 			<xs:enumeration value="CLDEMOTE" />
+			<xs:enumeration value="MCOMMIT" />
 			<xs:enumeration value="PREFETCH" />
 			<xs:enumeration value="PREFETCHW" />
 			<xs:enumeration value="PREFETCHWT1" />

diff --git a/opcodes/x86_64.py b/opcodes/x86_64.py
@@ -506,6 +506,7 @@ class ISAExtension:
         - "CLWB"             := The `CLWB` instruction.
         - "CLZERO"           := The `CLZERO` instruction.
         - "CLDEMOTE"         := The `CLDEMOTE` instruction.
+        - "MCOMMIT"          := The `MCOMMIT` instruction.
         - "PREFETCH"         := The `PREFETCH` instruction (3dnow! Prefetch).
         - "PREFETCHI"        := The `PREFETCHIT0`/`PREFETCHIT1` instructions.
         - "PREFETCHW"        := The `PREFETCHW` instruction (3dnow! Prefetch/Intel PRFCHW).

diff --git a/opcodes/x86_64.xml b/opcodes/x86_64.xml
@@ -9842,6 +9842,17 @@
       </Encoding>
     </InstructionForm>
   </Instruction>
+  <Instruction name="MCOMMIT" summary="Memory COMMIT">
+    <InstructionForm gas-name="mcommit">
+      <ISA id="MCOMMIT"/>
+      <Encoding>
+        <Prefix byte="F3" mandatory="true"/>
+        <Opcode byte="0F"/>
+        <Opcode byte="01"/>
+        <Opcode byte="FA"/>
+      </Encoding>
+    </InstructionForm>
+  </Instruction>
   <Instruction name="MFENCE" summary="Memory Fence">
     <InstructionForm gas-name="mfence" go-name="MFENCE" nacl-version="33">
       <ISA id="SSE2"/>

diff --git a/opcodes/x86_64.xsd b/opcodes/x86_64.xsd
@@ -464,6 +464,7 @@
 			<xs:enumeration value="CLWB" />
 			<xs:enumeration value="CLZERO" />
 			<xs:enumeration value="CLDEMOTE" />
+			<xs:enumeration value="MCOMMIT" />
 			<xs:enumeration value="PREFETCH" />
 			<xs:enumeration value="PREFETCHI" />
 			<xs:enumeration value="PREFETCHW" />