update l2 cache line size note for mi300

ROCm · Jan 22, 2025 · d72d1aa · d72d1aa
1 parent 809ebb9
commit d72d1aa
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/docs/conceptual/l2-cache.rst b/docs/conceptual/l2-cache.rst
@@ -284,9 +284,9 @@ This section details the incoming requests to the L2 cache from the
 .. note::
 
    All requests to the L2 are for a single cache line's worth of data. The size
-   of a cache line may vary depending on the accelerator, however on an AMD
-   Instinct CDNA2 :ref:`MI200 <mixxx-note>` accelerator, it is 128B, while on
-   an MI100, it is 64B.
+   of a cache line may vary depending on the accelerator. The L2 cache line
+   size is 128B on :ref:`MI300 and MI200 <mixxx-note>` accelerators, while on
+   MI100, it is 64B.
 
 .. _l2-fabric: