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1. LLC-cache-simulator LLC-cache-simulator Public

   A SystemVerilog-based simulation and design of a Last Level Cache (LLC) implementing the MESI protocol, featuring Pseudo-LRU replacement, multi-mode simulations, and comprehensive testing strategie…

   SystemVerilog 4 1

2. siddharth23-8/32-bit-RISC-V-Cpu-Core siddharth23-8/32-bit-RISC-V-Cpu-Core Public

   Python 32 2

3. CMOS-NOR-Gate_IITH-Hackathon CMOS-NOR-Gate_IITH-Hackathon Public

   CMOS Implemented NOR Gate is designed using Synopsys custom design tools.

4. Satya7733/Asyc_FIFO Satya7733/Asyc_FIFO Public

   This project contains asynchronous FIFO in System Verilog Design and Verification done in Class Based Verification and UVM

   2