Pyxsi enablement for alternative rtl simulation

docker/Dockerfile.finn

@@ -65,12 +65,18 @@ RUN apt-get update && \
     python-is-python3 \
     python3-pip \
     python3-setuptools-scm \
-    python3-venv
+    python3-venv \
+    pybind11-dev \
+    libfmt-dev \
+    libboost-dev \
+    libjansson-dev \
+    libgetdata-dev \
+    libtinfo5
 RUN echo "StrictHostKeyChecking no" >> /etc/ssh/ssh_config
 RUN locale-gen "en_US.UTF-8"
 
 # install Verilator from source to get the right version
-RUN apt-get install -y git perl make autoconf g++ flex bison ccache libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g zlib1g-dev
+RUN apt-get install -y git perl make autoconf g++-10 flex bison ccache libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g zlib1g-dev
 RUN git clone https://github.com/verilator/verilator
 RUN cd verilator && \
     git checkout v4.224 && \

docker/finn_entrypoint.sh

@@ -105,6 +105,22 @@ else
   fi
 fi
 
+if [ -z "${XILINX_VIVADO}" ]; then
+  yecho "pyxsi will be unavailable since Vivado was not found"
+else
+  if [ -f "${FINN_ROOT}/deps/pyxsi/pyxsi.so" ]; then
+    gecho "Found pyxsi at ${FINN_ROOT}/deps/pyxsi/pyxsi.so"
+  else
+    OLDPWD=$(pwd)
+    cd ${FINN_ROOT}/deps/pyxsi
+    touch .dockerenv
+    make
+    cd $OLDPWD
+  fi
+  export PYTHONPATH=$PYTHONPATH:${FINN_ROOT}/deps/pyxsi:${FINN_ROOT}/deps/pyxsi/py
+  export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/lib/x86_64-linux-gnu/:${XILINX_VIVADO}/lib/lnx64.o
+fi
+
 if [ -f "$HLS_PATH/settings64.sh" ];then
   # source Vitis HLS env.vars
   source $HLS_PATH/settings64.sh
@@ -129,6 +145,7 @@ if [ -d "$FINN_ROOT/.Xilinx" ]; then
     mkdir "$HOME/.Xilinx/Vivado/"
     cp "$FINN_ROOT/.Xilinx/Vivado/Vivado_init.tcl" "$HOME/.Xilinx/Vivado/"
     gecho "Found Vivado_init.tcl and copied to $HOME/.Xilinx/Vivado/Vivado_init.tcl"
+
   else
     yecho "Unable to find $FINN_ROOT/.Xilinx/Vivado/Vivado_init.tcl"
   fi

docker/jenkins/Jenkinsfile

@@ -313,15 +313,15 @@ void createMultiMarkerScript(String markers, String testResultsFilename, String
   // Passing multiple markers when running ./run-docker.sh does not work with bash.
   // Therefore, create a script to maintain the single quotes that surround the markers
   sh """echo "#!/bin/bash
-python -m pytest -m \'${markers}\' --junitxml=${testResultsFilename}.xml --html=${testResultsFilename}.html --self-contained-html ${additionalOptions}" >> run-tests.sh
+python -m pytest -m \'${markers}\' --forked --junitxml=${testResultsFilename}.xml --html=${testResultsFilename}.html --self-contained-html ${additionalOptions}" >> run-tests.sh
     """
 
   // Give permissions to script
   sh 'chmod 777 run-tests.sh'
 }
 
 void runDockerPytestWithMarker(String marker, String testResultsFilename, String additionalOptions) {
-  sh """./run-docker.sh python -m pytest -m ${marker} --junitxml=${testResultsFilename}.xml --html=${testResultsFilename}.html --self-contained-html ${additionalOptions}"""
+  sh """./run-docker.sh python -m pytest -m ${marker} --forked --junitxml=${testResultsFilename}.xml --html=${testResultsFilename}.html --self-contained-html ${additionalOptions}"""
 }
 
 def findBoardBuildFiles(String searchDir, String dirToFind) {

fetch-repos.sh

@@ -39,6 +39,7 @@ XIL_BDF_COMMIT="8cf4bb674a919ac34e3d99d8d71a9e60af93d14e"
 RFSOC4x2_BDF_COMMIT="13fb6f6c02c7dfd7e4b336b18b959ad5115db696"
 KV260_BDF_COMMIT="98e0d3efc901f0b974006bc4370c2a7ad8856c79"
 EXP_BOARD_FILES_MD5="226ca927a16ea4ce579f1332675e9e9a"
+PYXSI_COMMIT="4f4ec10a3631c4c44b5bc0ede698d41c924d2b86"
 
 QONNX_URL="https://github.com/fastmachinelearning/qonnx.git"
 FINN_EXP_URL="https://github.com/Xilinx/finn-experimental.git"
@@ -51,6 +52,7 @@ AVNET_BDF_URL="https://github.com/Avnet/bdf.git"
 XIL_BDF_URL="https://github.com/Xilinx/XilinxBoardStore.git"
 RFSOC4x2_BDF_URL="https://github.com/RealDigitalOrg/RFSoC4x2-BSP.git"
 KV260_BDF_URL="https://github.com/Xilinx/XilinxBoardStore.git"
+PYXSI_URL="https://github.com/maltanar/pyxsi.git"
 
 QONNX_DIR="qonnx"
 FINN_EXP_DIR="finn-experimental"
@@ -63,6 +65,7 @@ AVNET_BDF_DIR="avnet-bdf"
 XIL_BDF_DIR="xil-bdf"
 RFSOC4x2_BDF_DIR="rfsoc4x2-bdf"
 KV260_SOM_BDF_DIR="kv260-som-bdf"
+PYXSI_DIR="pyxsi"
 
 # absolute path to this script, e.g. /home/user/bin/foo.sh
 SCRIPT=$(readlink -f "$0")
@@ -126,6 +129,7 @@ fetch_repo $AVNET_BDF_URL $AVNET_BDF_COMMIT $AVNET_BDF_DIR
 fetch_repo $XIL_BDF_URL $XIL_BDF_COMMIT $XIL_BDF_DIR
 fetch_repo $RFSOC4x2_BDF_URL $RFSOC4x2_BDF_COMMIT $RFSOC4x2_BDF_DIR
 fetch_repo $KV260_BDF_URL $KV260_BDF_COMMIT $KV260_SOM_BDF_DIR
+fetch_repo $PYXSI_URL $PYXSI_COMMIT $PYXSI_DIR
 
 # Can skip downloading of board files entirely if desired
 if [ "$FINN_SKIP_BOARD_FILES" = "1" ]; then

finn-rtllib/swg/swg_template_wrapper.v

@@ -71,4 +71,8 @@ $TOP_MODULE_NAME$_impl #(
 	.out_V_V_TREADY(out_V_TREADY)
 );
 
+if (OUT_WIDTH_PADDED > BUF_OUT_WIDTH) begin
+	assign out_V_TDATA[OUT_WIDTH_PADDED-1:BUF_OUT_WIDTH] = {(OUT_WIDTH_PADDED-BUF_OUT_WIDTH){1'b0}};
+end
+
 endmodule : $TOP_MODULE_NAME$

finn-rtllib/swg/swg_template_wrapper_dynamic.v

@@ -180,4 +180,8 @@ $TOP_MODULE_NAME$_impl #(
     .cfg_last_write(cfg_last_write)
 );
 
+if (OUT_WIDTH_PADDED > BUF_OUT_WIDTH) begin
+       assign out_V_TDATA[OUT_WIDTH_PADDED-1:BUF_OUT_WIDTH] = {(OUT_WIDTH_PADDED-BUF_OUT_WIDTH){1'b0}};
+end
+
 endmodule : $TOP_MODULE_NAME$

finn-rtllib/thresholding/hdl/thresholding_axi.sv

@@ -191,7 +191,10 @@ module thresholding_axi #(
 		.cfg_rack, .cfg_q,
 
 		.irdy(s_axis_tready), .ivld(s_axis_tvalid), .idat,
-		.ordy(m_axis_tready), .ovld(m_axis_tvalid), .odat(m_axis_tdata)
+		.ordy(m_axis_tready), .ovld(m_axis_tvalid), .odat(m_axis_tdata[PE*O_BITS-1:0])
 	);
+	if($bits(m_axis_tdata) > PE*O_BITS) begin : genPadOut
+		assign	m_axis_tdata[$left(m_axis_tdata):PE*O_BITS] = '0;
+	end : genPadOut
 
 endmodule : thresholding_axi

finn-rtllib/thresholding/sim/thresholding_axi_tb.sv

@@ -232,7 +232,7 @@ module thresholding_axi_tb #(
 			end
 		join_any
 		done <= 1;
-		repeat(N+6)  @(posedge clk);
+		repeat(2*N+8)  @(posedge clk);
 
 		assert(QW.size() == 0) else begin
 			$error("Missing %0d outputs.", QW.size());

notebooks/end2end_example/bnn-pynq/tfc_end2end_verification.ipynb

@@ -404,6 +404,7 @@
     "child_model = child_model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns))\n",
     "child_model = child_model.transform(PrepareRTLSim())\n",
     "child_model.set_metadata_prop(\"exec_mode\",\"rtlsim\")\n",
+    "child_model.set_metadata_prop(\"rtlsim_backend\",\"pyxsi\")\n",
     "child_model.save(build_dir + \"/tfc_w1_a1_dataflow_child.onnx\");"
    ]
   },

requirements.txt

@@ -12,6 +12,7 @@ pre-commit==3.3.2
 protobuf==3.20.3
 psutil==5.9.4
 pyscaffold==4.4
+pytest-forked==1.6.0
 scipy==1.10.1
 setupext-janitor>=1.1.2
 sigtools==4.0.1

src/finn/builder/build_dataflow_config.py

@@ -281,6 +281,14 @@ class DataflowBuildConfig:
     #: Only relevant when `auto_fifo_depths = True`
     large_fifo_mem_style: Optional[LargeFIFOMemStyle] = LargeFIFOMemStyle.AUTO
 
+    #: Enable input throttling for simulation-based FIFO sizing
+    #: Only relevant if auto_fifo_strategy = LARGEFIFO_RTLSIM
+    fifosim_input_throttle: Optional[bool] = True
+
+    #: Enable saving waveforms from simulation-based FIFO sizing
+    #: Only relevant if auto_fifo_strategy = LARGEFIFO_RTLSIM
+    fifosim_save_waveform: Optional[bool] = False
+
     #: Target clock frequency (in nanoseconds) for Vitis HLS synthesis.
     #: e.g. `hls_clk_period_ns=5.0` will target a 200 MHz clock.
     #: If not specified it will default to synth_clk_period_ns

src/finn/builder/build_dataflow_steps.py

@@ -109,6 +109,7 @@
     InsertAndSetFIFODepths,
     RemoveShallowFIFOs,
     SplitLargeFIFOs,
+    xsi_fifosim,
 )
 from finn.transformation.fpgadataflow.set_folding import SetFolding
 from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers
@@ -126,7 +127,6 @@
     get_rtlsim_trace_depth,
     pyverilate_get_liveness_threshold_cycles,
 )
-from finn.util.pyverilator import verilator_fifosim
 from finn.util.test import execute_parent
 
 
@@ -250,6 +250,8 @@ def prepare_for_stitched_ip_rtlsim(verify_model, cfg):
     # set top-level prop for stitched-ip rtlsim and launch
     verify_model.set_metadata_prop("exec_mode", "rtlsim")
     # TODO make configurable
+    verify_model.set_metadata_prop("rtlsim_backend", "pyxsi")
+    # TODO make configurable
     # verify_model.set_metadata_prop("rtlsim_trace", "trace.vcd")
     return verify_model
 
@@ -583,15 +585,21 @@ def step_set_fifo_depths(model: ModelWrapper, cfg: DataflowBuildConfig):
                     "Multi-in/out streams currently not supported "
                     + "in FINN C++ verilator driver, falling back to Python"
                 )
+            if cfg.fifosim_save_waveform:
+                model.set_metadata_prop("rtlsim_trace", "fifosim_trace.wdb")
             model = model.transform(
                 InsertAndSetFIFODepths(
                     cfg._resolve_fpga_part(),
                     cfg._resolve_hls_clk_period(),
                     swg_exception=cfg.default_swg_exception,
                     vivado_ram_style=cfg.large_fifo_mem_style,
                     force_python_sim=force_python_sim,
+                    fifosim_input_throttle=cfg.fifosim_input_throttle,
                 )
             )
+            if cfg.fifosim_save_waveform:
+                # un-set rtlsim_trace to remove unwanted traces in later steps
+                model.set_metadata_prop("rtlsim_trace", "")
             # InsertAndSetFIFODepths internally removes any shallow FIFOs
             # so no need to call RemoveShallowFIFOs here
         else:
@@ -719,7 +727,7 @@ def step_measure_rtlsim_performance(model: ModelWrapper, cfg: DataflowBuildConfi
             rtlsim_perf_dict = throughput_test_rtlsim(rtlsim_model, rtlsim_bs)
             rtlsim_perf_dict["latency_cycles"] = rtlsim_latency_dict["cycles"]
         else:
-            rtlsim_perf_dict = verilator_fifosim(model, rtlsim_bs)
+            rtlsim_perf_dict = xsi_fifosim(model, rtlsim_bs)
             # keep keys consistent between the Python and C++-styles
             cycles = rtlsim_perf_dict["cycles"]
             clk_ns = float(model.get_metadata_prop("clk_ns"))

src/finn/core/onnx_exec.py

@@ -52,44 +52,38 @@ def execute_onnx(model, input_dict, return_full_exec_context=False, start_node=N
     model_exec_mode = model.get_metadata_prop("exec_mode")
     if (model_exec_mode is None) or (model_exec_mode == ""):
         return execute_onnx_base(model, input_dict, return_full_exec_context, start_node, end_node)
+    elif model_exec_mode == "rtlsim":
+        # check sanity of model and then use stitched IP for rtlsim
+        if not model.check_all_tensor_shapes_specified():
+            raise Exception("Found unspecified tensor shapes, try infer_shapes")
+        ret = model.analysis(ta.nodes_topologically_sorted)
+        assert (
+            ret["nodes_topologically_sorted"] is True
+        ), """Nodes must be
+        topologically sorted."""
 
-    if not model.check_all_tensor_shapes_specified():
-        raise Exception("Found unspecified tensor shapes, try infer_shapes")
-    ret = model.analysis(ta.nodes_topologically_sorted)
-    assert (
-        ret["nodes_topologically_sorted"] is True
-    ), """Nodes must be
-    topologically sorted."""
-
-    graph = model.graph
-    # first, we need to make sure that every variable required by the graph has
-    # some buffer associated with it. this includes graph inputs (which includes
-    # the input data as well as the trained parameters) and the graph ValueInfo
-    # (intermediate tensors between layers)
-    # this is provided by the execution_context, which is a dict of np.ndarray
-    execution_context = model.make_empty_exec_context()
-    # fill in any inputs provided to this function
-    for inp_name in input_dict.keys():
-        if inp_name in execution_context:
-            if execution_context[inp_name].shape == input_dict[inp_name].shape:
-                execution_context[inp_name] = input_dict[inp_name]
-            else:
-                raise Exception(
-                    "Shape mismatch for provided input %s: found %s expected %s "
-                    % (
-                        inp_name,
-                        str(execution_context[inp_name].shape),
-                        str(input_dict[inp_name].shape),
+        graph = model.graph
+        # first, we need to make sure that every variable required by the graph has
+        # some buffer associated with it. this includes graph inputs (which includes
+        # the input data as well as the trained parameters) and the graph ValueInfo
+        # (intermediate tensors between layers)
+        # this is provided by the execution_context, which is a dict of np.ndarray
+        execution_context = model.make_empty_exec_context()
+        # fill in any inputs provided to this function
+        for inp_name in input_dict.keys():
+            if inp_name in execution_context:
+                if execution_context[inp_name].shape == input_dict[inp_name].shape:
+                    execution_context[inp_name] = input_dict[inp_name]
+                else:
+                    raise Exception(
+                        "Shape mismatch for provided input %s: found %s expected %s "
+                        % (
+                            inp_name,
+                            str(execution_context[inp_name].shape),
+                            str(input_dict[inp_name].shape),
+                        )
                     )
-                )
 
-    # check if model has an execution mode set
-    # if None, execute model node by node using execute_node()
-    # if set to "rtlsim" execute model using pyverilator
-    model_exec_mode = model.get_metadata_prop("exec_mode")
-    if (model_exec_mode is None) or (model_exec_mode == ""):
-        return execute_onnx_base()
-    elif model_exec_mode == "rtlsim":
         # use stitched IP for rtlsim
         rtlsim_exec(model, execution_context)
     else: