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Single-cycle and multi-cycle MIPS processor designs implemented in Verilog

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Name		Name	Last commit message	Last commit date
Latest commit History 11 Commits
multi_cycle_MIPS		multi_cycle_MIPS
single_cycle_MIPS		single_cycle_MIPS
README.md		README.md

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MIPS-designs

🏃 Usage

I recommand using VSCode + iverilog to develop this project.

Firstly use iverilog to generate .out file

iverilog -o .\build\test.out .\tests\test.v .\src\mips.v

Then convert .out file to .vcd file

vvp .\build\test.out

Finally use gtkwave to open and analyze .vcd file

gtkwave.exe .\build\test.vcd

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Single-cycle and multi-cycle MIPS processor designs implemented in Verilog

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