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Remove Deref from peripheral singletons
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@bugadani
bugadani committed Jan 15, 2025
1 parent e6c38c5 commit 7deaba6
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Showing 140 changed files with 3,225 additions and 3,041 deletions.
44 changes: 31 additions & 13 deletions esp-hal/src/aes/esp32.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,22 +13,31 @@ impl Aes<'_> {
}

pub(super) fn write_key(&mut self, key: &[u8]) {
let key_len = self.aes.key_iter().count();
let key_len = self.aes.register_block().key_iter().count();
debug_assert!(key.len() <= key_len * ALIGN_SIZE);
debug_assert_eq!(key.len() % ALIGN_SIZE, 0);
self.alignment_helper
.volatile_write_regset(self.aes.key(0).as_ptr(), key, key_len);
self.alignment_helper.volatile_write_regset(
self.aes.register_block().key(0).as_ptr(),
key,
key_len,
);
}

pub(super) fn write_block(&mut self, block: &[u8]) {
let text_len = self.aes.text_iter().count();
let text_len = self.aes.register_block().text_iter().count();
debug_assert_eq!(block.len(), text_len * ALIGN_SIZE);
self.alignment_helper
.volatile_write_regset(self.aes.text(0).as_ptr(), block, text_len);
self.alignment_helper.volatile_write_regset(
self.aes.register_block().text(0).as_ptr(),
block,
text_len,
);
}

pub(super) fn write_mode(&self, mode: Mode) {
self.aes.mode().write(|w| unsafe { w.bits(mode as _) });
self.aes
.register_block()
.mode()
.write(|w| unsafe { w.bits(mode as _) });
}

/// Configures how the state matrix would be laid out
Expand All @@ -48,22 +57,31 @@ impl Aes<'_> {
to_write |= (input_text_word_endianess as u32) << 3;
to_write |= (output_text_byte_endianess as u32) << 4;
to_write |= (output_text_word_endianess as u32) << 5;
self.aes.endian().write(|w| unsafe { w.bits(to_write) });
self.aes
.register_block()
.endian()
.write(|w| unsafe { w.bits(to_write) });
}

pub(super) fn write_start(&self) {
self.aes.start().write(|w| w.start().set_bit());
self.aes
.register_block()
.start()
.write(|w| w.start().set_bit());
}

pub(super) fn read_idle(&mut self) -> bool {
self.aes.idle().read().idle().bit_is_set()
self.aes.register_block().idle().read().idle().bit_is_set()
}

pub(super) fn read_block(&self, block: &mut [u8]) {
let text_len = self.aes.text_iter().count();
let text_len = self.aes.register_block().text_iter().count();
debug_assert_eq!(block.len(), text_len * ALIGN_SIZE);
self.alignment_helper
.volatile_read_regset(self.aes.text(0).as_ptr(), block, text_len);
self.alignment_helper.volatile_read_regset(
self.aes.register_block().text(0).as_ptr(),
block,
text_len,
);
}
}

Expand Down
41 changes: 28 additions & 13 deletions esp-hal/src/aes/esp32cX.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,41 +6,56 @@ impl Aes<'_> {
}

fn write_dma(&mut self, enable_dma: bool) {
match enable_dma {
true => self.aes.dma_enable().write(|w| w.dma_enable().set_bit()),
false => self.aes.dma_enable().write(|w| w.dma_enable().clear_bit()),
};
self.aes
.register_block()
.dma_enable()
.write(|w| w.dma_enable().bit(enable_dma));
}

pub(super) fn write_key(&mut self, key: &[u8]) {
debug_assert!(key.len() <= 8 * ALIGN_SIZE);
debug_assert_eq!(key.len() % ALIGN_SIZE, 0);
self.alignment_helper
.volatile_write_regset(self.aes.key(0).as_ptr(), key, 8);
self.alignment_helper.volatile_write_regset(
self.aes.register_block().key(0).as_ptr(),
key,
8,
);
}

pub(super) fn write_block(&mut self, block: &[u8]) {
debug_assert_eq!(block.len(), 4 * ALIGN_SIZE);
self.alignment_helper
.volatile_write_regset(self.aes.text_in(0).as_ptr(), block, 4);
self.alignment_helper.volatile_write_regset(
self.aes.register_block().text_in(0).as_ptr(),
block,
4,
);
}

pub(super) fn write_mode(&self, mode: Mode) {
self.aes.mode().write(|w| unsafe { w.bits(mode as _) });
self.aes
.register_block()
.mode()
.write(|w| unsafe { w.bits(mode as _) });
}

pub(super) fn write_start(&self) {
self.aes.trigger().write(|w| w.trigger().set_bit());
self.aes
.register_block()
.trigger()
.write(|w| w.trigger().set_bit());
}

pub(super) fn read_idle(&mut self) -> bool {
self.aes.state().read().state().bits() == 0
self.aes.register_block().state().read().state().bits() == 0
}

pub(super) fn read_block(&self, block: &mut [u8]) {
debug_assert_eq!(block.len(), 4 * ALIGN_SIZE);
self.alignment_helper
.volatile_read_regset(self.aes.text_out(0).as_ptr(), block, 4);
self.alignment_helper.volatile_read_regset(
self.aes.register_block().text_out(0).as_ptr(),
block,
4,
);
}
}

Expand Down
35 changes: 24 additions & 11 deletions esp-hal/src/aes/esp32s2.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,30 +15,37 @@ impl Aes<'_> {

fn write_dma(&mut self, enable_dma: bool) {
self.aes
.register_block()
.dma_enable()
.write(|w| w.dma_enable().bit(enable_dma));
}

pub(super) fn write_key(&mut self, key: &[u8]) {
let key_len = self.aes.key_iter().count();
let key_len = self.aes.register_block().key_iter().count();
debug_assert!(key.len() <= key_len * ALIGN_SIZE);
debug_assert_eq!(key.len() % ALIGN_SIZE, 0);
self.alignment_helper
.volatile_write_regset(self.aes.key(0).as_ptr(), key, key_len);
self.alignment_helper.volatile_write_regset(
self.aes.register_block().key(0).as_ptr(),
key,
key_len,
);
}

pub(super) fn write_block(&mut self, block: &[u8]) {
let text_in_len = self.aes.text_in_iter().count();
let text_in_len = self.aes.register_block().text_in_iter().count();
debug_assert_eq!(block.len(), text_in_len * ALIGN_SIZE);
self.alignment_helper.volatile_write_regset(
self.aes.text_in(0).as_ptr(),
self.aes.register_block().text_in(0).as_ptr(),
block,
text_in_len,
);
}

pub(super) fn write_mode(&self, mode: Mode) {
self.aes.mode().write(|w| unsafe { w.bits(mode as _) });
self.aes
.register_block()
.mode()
.write(|w| unsafe { w.bits(mode as _) });
}

/// Configures how the state matrix would be laid out.
Expand All @@ -58,22 +65,28 @@ impl Aes<'_> {
to_write |= (input_text_word_endianess as u32) << 3;
to_write |= (output_text_byte_endianess as u32) << 4;
to_write |= (output_text_word_endianess as u32) << 5;
self.aes.endian().write(|w| unsafe { w.bits(to_write) });
self.aes
.register_block()
.endian()
.write(|w| unsafe { w.bits(to_write) });
}

pub(super) fn write_start(&self) {
self.aes.trigger().write(|w| w.trigger().set_bit());
self.aes
.register_block()
.trigger()
.write(|w| w.trigger().set_bit());
}

pub(super) fn read_idle(&mut self) -> bool {
self.aes.state().read().state().bits() == 0
self.aes.register_block().state().read().state().bits() == 0
}

pub(super) fn read_block(&self, block: &mut [u8]) {
let text_out_len = self.aes.text_out_iter().count();
let text_out_len = self.aes.register_block().text_out_iter().count();
debug_assert_eq!(block.len(), text_out_len * ALIGN_SIZE);
self.alignment_helper.volatile_read_regset(
self.aes.text_out(0).as_ptr(),
self.aes.register_block().text_out(0).as_ptr(),
block,
text_out_len,
);
Expand Down
30 changes: 20 additions & 10 deletions esp-hal/src/aes/esp32s3.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,45 +7,55 @@ impl Aes<'_> {

fn write_dma(&mut self, enable_dma: bool) {
self.aes
.register_block()
.dma_enable()
.write(|w| w.dma_enable().bit(enable_dma));
}

pub(super) fn write_key(&mut self, key: &[u8]) {
let key_len = self.aes.key_iter().count();
let key_len = self.aes.register_block().key_iter().count();
debug_assert!(key.len() <= key_len * ALIGN_SIZE);
debug_assert_eq!(key.len() % ALIGN_SIZE, 0);
self.alignment_helper
.volatile_write_regset(self.aes.key(0).as_ptr(), key, key_len);
self.alignment_helper.volatile_write_regset(
self.aes.register_block().key(0).as_ptr(),
key,
key_len,
);
}

pub(super) fn write_block(&mut self, block: &[u8]) {
let text_in_len = self.aes.text_in_iter().count();
let text_in_len = self.aes.register_block().text_in_iter().count();
debug_assert_eq!(block.len(), text_in_len * ALIGN_SIZE);
self.alignment_helper.volatile_write_regset(
self.aes.text_in(0).as_ptr(),
self.aes.register_block().text_in(0).as_ptr(),
block,
text_in_len,
);
}

pub(super) fn write_mode(&self, mode: Mode) {
self.aes.mode().write(|w| unsafe { w.bits(mode as _) });
self.aes
.register_block()
.mode()
.write(|w| unsafe { w.bits(mode as _) });
}

pub(super) fn write_start(&self) {
self.aes.trigger().write(|w| w.trigger().set_bit());
self.aes
.register_block()
.trigger()
.write(|w| w.trigger().set_bit());
}

pub(super) fn read_idle(&mut self) -> bool {
self.aes.state().read().state().bits() == 0
self.aes.register_block().state().read().state().bits() == 0
}

pub(super) fn read_block(&self, block: &mut [u8]) {
let text_out_len = self.aes.text_out_iter().count();
let text_out_len = self.aes.register_block().text_out_iter().count();
debug_assert_eq!(block.len(), text_out_len * ALIGN_SIZE);
self.alignment_helper.volatile_read_regset(
self.aes.text_out(0).as_ptr(),
self.aes.register_block().text_out(0).as_ptr(),
block,
text_out_len,
);
Expand Down
46 changes: 31 additions & 15 deletions esp-hal/src/aes/mod.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -313,7 +313,7 @@ pub mod dma {

impl DmaSupport for AesDma<'_> {
fn peripheral_wait_dma(&mut self, _is_rx: bool, _is_tx: bool) {
while self.aes.aes.state().read().state().bits() != 2 // DMA status DONE == 2
while self.aes.aes.register_block().state().read().state().bits() != 2 // DMA status DONE == 2
&& !self.channel.tx.is_done()
{
// wait until done
Expand Down Expand Up @@ -451,22 +451,26 @@ pub mod dma {

#[cfg(any(esp32c3, esp32s2, esp32s3))]
fn reset_aes(&self) {
unsafe {
let s = crate::peripherals::SYSTEM::steal();
s.perip_rst_en1()
.modify(|_, w| w.crypto_aes_rst().set_bit());
s.perip_rst_en1()
.modify(|_, w| w.crypto_aes_rst().clear_bit());
}
use crate::peripherals::SYSTEM;

SYSTEM::regs()
.perip_rst_en1()
.modify(|_, w| w.crypto_aes_rst().set_bit());
SYSTEM::regs()
.perip_rst_en1()
.modify(|_, w| w.crypto_aes_rst().clear_bit());
}

#[cfg(any(esp32c6, esp32h2))]
fn reset_aes(&self) {
unsafe {
let s = crate::peripherals::PCR::steal();
s.aes_conf().modify(|_, w| w.aes_rst_en().set_bit());
s.aes_conf().modify(|_, w| w.aes_rst_en().clear_bit());
}
use crate::peripherals::PCR;

PCR::regs()
.aes_conf()
.modify(|_, w| w.aes_rst_en().set_bit());
PCR::regs()
.aes_conf()
.modify(|_, w| w.aes_rst_en().clear_bit());
}

fn dma_peripheral(&self) -> DmaPeripheral {
Expand All @@ -476,23 +480,30 @@ pub mod dma {
fn enable_dma(&self, enable: bool) {
self.aes
.aes
.register_block()
.dma_enable()
.write(|w| w.dma_enable().bit(enable));
}

fn enable_interrupt(&self) {
self.aes.aes.int_ena().write(|w| w.int_ena().set_bit());
self.aes
.aes
.register_block()
.int_ena()
.write(|w| w.int_ena().set_bit());
}

fn set_cipher_mode(&self, mode: CipherMode) {
self.aes
.aes
.register_block()
.block_mode()
.modify(|_, w| unsafe { w.block_mode().bits(mode as u8) });

if mode == CipherMode::Ctr {
self.aes
.aes
.register_block()
.inc_sel()
.modify(|_, w| w.inc_sel().clear_bit());
}
Expand All @@ -503,14 +514,19 @@ pub mod dma {
}

fn finish_transform(&self) {
self.aes.aes.dma_exit().write(|w| w.dma_exit().set_bit());
self.aes
.aes
.register_block()
.dma_exit()
.write(|w| w.dma_exit().set_bit());
self.enable_dma(false);
self.reset_aes();
}

fn set_num_block(&self, block: u32) {
self.aes
.aes
.register_block()
.block_num()
.modify(|_, w| unsafe { w.block_num().bits(block) });
}
Expand Down
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