Firtool Release 1.36.0

What's Changed

• [FIRRTL] RefConnect for references by @darthscsi in #4798
• [PyCDE] Include capnp, kj libs in wheel by @teqdruid in #4799
• [Arc] Add deduplication pass by @fabianschuiki in #4698
• [Arc] Add module force-inlining pass by @fabianschuiki in #4699
• [Arc] Add arcilator convenience tool by @fabianschuiki in #4700
• [FIRRTL][InferWidths] Honor upper bounds on AttachOp by @fabianschuiki in #4796
• [PyCDE] Package collateral SV and binaries by @teqdruid in #4808
• Bump LLVM by @azidar in #4805
• [ExportVerilog] Avoid splitting wire decl and assign in expr inlining by @fabianschuiki in #4819
• [firtool] Remove many unsued CL options by @youngar in #4820
• [HW] Allow inlining of all constant and aggregate ops. by @jopperm in #4506
• [Support] Add ImplicitSSAName directive for string attributes by @fabianschuiki in #4821
• [HW] Add hw.wire operation by @fabianschuiki in #4822
• [ExportVerilog] Add hw.wire emission support by @fabianschuiki in #4823
• [FIRRTLToHW] Lower FIRRTL node to HW wire by @fabianschuiki in #4824
• [Arc] Add loop splitting pass by @fabianschuiki in #4714
• [Arc] Add constant sinking pass by @fabianschuiki in #4715
• [Arc] Add lookup table generation pass by @fabianschuiki in #4682
• [Arc] Add makeshift input preprocessing by @fabianschuiki in #4683
• [Arc] Add variadic op simplification pass by @fabianschuiki in #4724
• [Arc] Add pass to remove unused arc arguments by @fabianschuiki in #4725
• [Arc] Add lookup table op and lowering pass by @fabianschuiki in #4726
• [Arc] Add simple arc inlining pass by @fabianschuiki in #4727
• [Arc] Add Comb to MLIR Arith conversion pass by @fabianschuiki in #4728
• [FIRRTL] F{Ext,Int}Module: build with parameters, internalPaths. by @dtzSiFive in #4829
• [Arc] Add tap op to observe ports/wires and AddTaps pass by @fabianschuiki in #4684
• [SCFToCalyx] Read "calyx.port_name" Attribute from FuncOp arguments/results by @xerpi in #4841
• [FIRRTL][CheckCombLoops] Improve loop reporting diagnostics. by @dtzSiFive in #4847
• [HWMemSimSimpl] Add rw_addr_collision = yes to memories with registered read addresses by @nandor in #4852
• [IMCP] Make field sensitive by @uenoku in #4795
• [Arc] Remove unobservable StateOps by @maerhart in #4810
• [reduce] Fix crash on nested ops; fix poor scaling of module op counting by @fabianschuiki in #4860
• [OM] Initial implementation of the OM dialect. by @mikeurbach in #4836
• Do not use non-const lvalue-refs with enumerate by @albertchen-sifive in #4855
• [Arc] SplitLoops: process splits in dependency order by @maerhart in #4865
• [Docs] Add recommended LoweringOptions by target by @uenoku in #4854
• [FIRParser] Don't try to parse LPKEYWORD as primitive. by @dtzSiFive in #4861
• [ExportVerilog] Add lowering option to not emit version comment by @rsetaluri in #4811
• [FIRRLT] Narrow adds by @darthscsi in #4869

New Contributors

• @xerpi made their first contribution in #4841

Full Changelog: firtool-1.35.0...firtool-1.36.0