SiFive Internal Release 1.6.0

What's Changed

• [ExportVerilog] Add option to not emit location info by @rsetaluri in #3409
• [PrepareForEmission] Add a pass to run only PrepareForEmission by @uenoku in #3371
• Treat regreset the same in its initial lattice value as reg by @darthscsi in #3392
• Bump LLVM to cb69ba4faaf1de207b363b5198d33e29d0375e5d. by @richardxia in #3386
• Allow arbitrary order of idempotent or operations by @Schottkyc137 in #3416
• [FSM] Remove SingleBlockImplicitTerminator from StateOp, TransitionOp by @mortbopet in #3405
• [PyCDE,CAPI] Add support for the FSM dialect by @mortbopet in #3400
• [FIRRTL] Move the getInnerRefTo to a Utility by @prithayan in #3408
• [MSFT] AppID attribute by @teqdruid in #3425
• [FIRRTL] InnerSymbolTable: move to own header, add helpers by @dtzSiFive in #3407
• [SV] Add sv.attributes support to assign op by @uenoku in #3422
• [MSFT] Pass to discover AppIDs by @teqdruid in #3426
• [FIRRTL][GCSM] Use buffer wires for forced output ports by @youngar in #3431
• [FIRRTL] AnnotationDetails.h: be consistent, prefer constexpr [NFC] by @dtzSiFive in #3432

New Contributors

• @rsetaluri made their first contribution in #3409
• @Schottkyc137 made their first contribution in #3416

Full Changelog: sifive/1/5/1...sifive/1/6/0

SiFive Internal Release 1.5.1

What's Changed

• [PyCDE] Add @testmodule to reduce test boilerplate by @mortbopet in #3398
• [FIRRTL] Add helper utility to get InnerSym name. NFC. by @prithayan in #3406
• [PyCDE] Switch back to normal Type function by @teqdruid in #3412
• [FIRRTL] touchup EmitOMIR test so symbol names are checked by @dtzSiFive in #3410
• [PyCDE] Clock inputs and clocking blocks by @teqdruid in #3413
• [FIRRTL] Fix bug in GCT Taps XMRs by @seldridge in #3415

Full Changelog: sifive/1/5/0...sifive/1/5/1

SiFive Internal Release 1.5.0

What's Changed

• [PyCDE] Add Matrix class by @mortbopet in #3369
• ExtractInstances: fix memory safety issue re:DenseMap by @dtzSiFive in #3385
• DropNames: Add statistic, fixup test by @dtzSiFive in #3379
• [FSM] Remove statetype from MachineOp by @mortbopet in #3382
• [PyCDE] Make module creation, generation generic by @mortbopet in #3383
• [Docs] Fix markdown link by @tymcauley in #3393
• [FIRRTL] Use Minimal XMRs in GCT Views by @seldridge in #3391
• [PyCDE] Improve various error messages by @mortbopet in #3376
• [PyCDE] Fix issue in slice index generation by @mortbopet in #3396
• [PyCDE] Flip NDArray before conversion by @mortbopet in #3395
• [FIRRTL] Set droppable names to temporary wires by @uenoku in #3399
• [FIRRTL] rework innerref verification, starting with HierPathOp. by @dtzSiFive in #3366
• [FIRRTL] EmitOMIR: Drop temporary HierPath's that may be invalid by @dtzSiFive in #3384
• [FIRRTL][Dedup] Pre-calculate the post-order of modules by @youngar in #3390
• [FIRRTL] Use relative XMRs in GCT Data/Mem Taps by @seldridge in #3401

Full Changelog: sifive/1/4/0...sifive/1/5/0

SiFive Internal Release 1.4.0

What's Changed

• [ExportVerilog] Add an option to enforce wires for expressions with namehint by @uenoku in #3292
• [LowerToHW] Fix bug with unmasked RW memory lowering by @prithayan in #3282
• [FIRRTL] Update GCT Taps to handle HierPathOp ending in Module by @prithayan in #3303
• [FIRRTL] Fix ModuleInliner to not rely on nonlocal BreadCrumbs by @prithayan in #3317
• [MSFT] Support for multiple top levels of same module by @teqdruid in #3321
• Bump LLVM to b59c2315a by @prithayan in #3293
• [Support] A few BackedgeBuilder improvements by @fabianschuiki in #3322
• [PyCDE] Add create methods for SV wire and assign ops by @mortbopet in #3332
• [PyCDE] Allow multiple or no results from op create methods by @mortbopet in #3333
• [SV] Replace StructAttrs with AttrDefs. NFC. by @prithayan in #3327
• Bump LLVM to b422dac24 by @mortbopet in #3335
• [FIRRTL] Update GrandCentral SignalMapping to handle HierPathOp ending on Module by @prithayan in #3304
• [FIRRTL] Update EmitOMIR for New NLA Style by @seldridge in #3336
• [FIRRTL] Update Dedup to handle HierPathOp ending on Module by @youngar in #3309
• [FIRRTL] Better node bypass in canonicalize. by @darthscsi in #3339
• [ExportVerilog] Verilog attribute support for sv.reg and sv.wire by @teqdruid in #3330
• [FIRRTL] Update InjectDUTHierarchy for new NLAs by @seldridge in #3331
• [PrepareForEmission] Don't copy namehint to all sub expressions by @uenoku in #3313
• [LowerToHW] Add BackedgeBuilder, directly materialize inst inputs by @fabianschuiki in #3323
• [FIRRTL] Fix doulbe free in FIRRTL node canonicalizer by @uenoku in #3346
• [FIRRTL] Remove old canonicalization patterns and fix NodeBypass by @darthscsi in #3348
• Fix Scheduling.md svg links by @makslevental in #3338
• [ExportVerilog] Collect names from declarations before expressions. by @mikeurbach in #3342
• [PyCDE][Python] Add support for InOutType by @mortbopet in #3343
• [Python] Add support for SV attributes by @teqdruid in #3349
• Revert "[ExportVerilog] Add an option to enforce wires for expressions with namehint" by @uenoku in #3354
• [FIRRTL] Make droppable_name default by @uenoku in #3344
• [FIRParser] Handle annotations on instance ports properly. by @dtzSiFive in #3355
• [FIRRTL] GrandCentralTaps: Fix use-after-free by @dtzSiFive in #3358
• [FIRRTL] ModuleInliner: new NLA support by @dtzSiFive in #3337
• [FIRRTL] Fix handling of new-style NLAs in ExtractInstances by @fabianschuiki in #3345
• [Calyx] Fix stack-use-after-scope (pointer to freed stack) by @dtzSiFive in #3359
• Add py-split-input-file for better python test support by @mortbopet in #3356
• [FIRRTL] PrefixModules: fix StringRef to temporary string by @dtzSiFive in #3361
• [FIRRTL] Update LowerMemory to handle HierPathOp ending in Module by @prithayan in #3306
• [FIRRTL] Fix mutate-while-iterate bug in Dedup by @tymcauley in #3364
• [Docs] Fix a few typos by @tymcauley in #3351
• [FIRRTL] Fix LowerTypes for non-NLA hierpaths by @seldridge in #3265
• [FIRRTL] Stop Adding DontTouch to GCT Views/Taps by @seldridge in #3353
• [FIRRTL] Fix double spaces after NameKind printer, NFC by @uenoku in #3370
• [StandardToHandshake] Expose removeBasicBlocks by @Dinistro in #3368
• [FIRRTL] Add inter-module DCE by @uenoku in #3324
• [FIRRTL][ModuleInliner] Check if nla in current path before renaming. by @prithayan in #3352

New Contributors

• @tymcauley made their first contribution in #3364

Full Changelog: sifive/1/3/0...sifive/1/4/0

Sifive Internal 1.3.0

What's Changed

• [SCFToCalyx] [StaticLogicToCalyx] Reduce templating in interfaces. by @cgyurgyik in #3274
• [SCFToCalyx] [StaticLogicToCalyx] Share passes. by @cgyurgyik in #3275
• [FIRRTL] Cannonicalize wires to nodes by @darthscsi in #3246
• [SCFToCalyx] [StaticLogicToCalyx] Share more passes. by @cgyurgyik in #3276
• [StandardToHandshake] Always emit extmemory, even when unused by @Dinistro in #3266
• [PyCDE] Type inference by @teqdruid in #3279
• Revert "[FIRRTL] Cannonicalize wires to nodes" by @mikeurbach in #3283
• [FIRRTL] Properly parse printf assertions with no message by @youngar in #3286
• [PyCDE] Syntactic sugar to support new subdesign by @teqdruid in #3288
• [CombFolds] Propagate sv.namehint attribute more aggressively by @uenoku in #3269
• [FIRRTLFolds] Propagate name attributes more aggresively by @uenoku in #3255
• [CI] Run the test builds in parallel by @teqdruid in #3278
• Improve documentation of attributes by @youngar in #3296
• [FIRRTL][Dedup] Add test for merging when blocks by @youngar in #3308
• [PrepareForEmission] Use namehint for spilled expression by @uenoku in #3297
• [FIRRTL] Split name preservation semantics into a dedicated attribute by @uenoku in #3247
• [FIRRTL] Update outdated comments and refactor parser related to NameKind, NFC by @uenoku in #3312
• [FIRRTL] Add DropNamePass by @uenoku in #3254
• [FIRRTL] Add cache to LowerAnnotations' annotation target resolution by @dtzSiFive in #3301
• [ExportVerilog] Add explicit bitcast for sub expressions by @uenoku in #3299
• [firtool] Rerun DropNamesPass after running middle-end passes by @uenoku in #3315
• [docs] NFC - Fix broken link to ExportVerilog.cpp by @emosy in #3318
• Fix for clion IDEA settings. by @sequencer in #3291

New Contributors

• @emosy made their first contribution in #3318

Full Changelog: sifive/1/2/0...sifive/1/3/0

Sifive Internal 1.2.0

What's Changed

• [FSM] Remove IsolatedFromAbove trait from fsm.machine by @mortbopet in #3212
• [SV] use module name for instantation name of extracted module by @dtzSiFive in #3252
• [CI] Build and cache seprate Clang and GCC builds of LLVM by @nandor in #3242
• [Handshake] Add missing lsq attribute to MemoryOp by @Dinistro in #3258
• [SCFToCalyx] [StaticLogicToCalyx] Continue separation of the conversions. by @cgyurgyik in #3243
• [FIRRTL] Improve error message of invalid connection flow by @youngar in #3231
• [FIRRTL] Clean up APInt usage in some folds by @youngar in #3233
• Bump LLVM to 4ad17d2e9 by @youngar in #3262
• [FIRRTL] Add support for emitting instance paths in signal driving by @dtzSiFive in #3259
• [FIRRTL] Fix bug in unmasked RW memory lowering by @prithayan in #3272
• [FIRRTL] Remove Update of breadcrumbs from GCT Taps Pass. NFC. by @prithayan in #3271
• [FIRRTL][IMConstProp] unique constants in module entry by @dtzSiFive in #3264

Full Changelog: sifive/1/1/0...sifive/1/2/0

Sifive Internal 1.1.0

What's Changed

• [FIRRTL] Fix use-after-free in SFCCompat register handling. by @mikeurbach in #3227
• [FIRParser] Fix bug extending an APInt to a smaller width by @youngar in #3226
• [HW] [ExportVerilog] Add parameter concat expression by @teqdruid in #3221
• [MSFT] Track instance hierarchy through module parameters by @teqdruid in #3229
• [llvm] bump by @nandor in #3168
• [AffineToStaticLogic] Generalize loop bound computation. by @mikeurbach in #3234
• [SCFToCalyx, Calyx, CalyxToHW] Add support for signed div and rem by @mortbopet in #3238
• [Calyx] Relax calyx.enable verifier by @mortbopet in #3211

Full Changelog: sifive/1/0/0...sifive/1/1/0

Sifive Internal Release 1.0.0

What's Changed

• [Support] Add iterator interface to SymbolCache by @mortbopet in #3142
• Temporarily stop printing version info in generated files by @youngar in #3169
• [NFC] Define InnerSymbol OpInterface and document rational in op by @darthscsi in #3119
• [PyCDE] [Python] Teach LocationVector bindings about 'None' for optional locations by @teqdruid in #3165
• [FIRRTL] Add utilities to NLATable analysis. NFC. by @prithayan in #3171
• [CMake] Make version generation opt-in by @uenoku in #3178
• [FIRRTL] NLATable: fixup and simplify a little, comments for doxygen by @dtzSiFive in #3181
• [FIRRTL] GCT View Scattering in LowerAnnotations by @seldridge in #3141
• [FIRRTL] basic support for subcircuit signal driving flows by @dtzSiFive in #3153
• [firtool] Only blackbox SRAMs when -repl-seq-mem is specified by @youngar in #3184
• Fix website generation for pass documentation by @youngar in #3185
• [Rational] Document inner symbol and references by @darthscsi in #3182
• [FIRRTL] Add Utilities to NLA and NLATable. NFC. by @prithayan in #3196
• [FIRRTL] Stop double-generating attribute docs by @youngar in #3188
• [Calyx] Add sign extension support by @mortbopet in #3189
• [docs] touchups by @dtzSiFive in #3194
• [FIRRTL] GCT Data/Mem Tap Scattering in LowerAnnotations by @seldridge in #3186
• [Calyx] Improve error handling in calyx emitter by @mortbopet in #3198
• [FIRRTL] Document baseline naming and what symbols imply by @darthscsi in #3197
• [CMake] Run git describe from the source dir, fix out-of-tree builds by @dtzSiFive in #3199
• [FIRRTL] Remove unused BlackBoxMemory pass by @youngar in #3187
• [FIRRTL] Simplify NonLocalAnchor namepath printing by @youngar in #3179
• [FIRRTL] Change Grand Central Views to use Wire Taps and Sink Constants by @seldridge in #3167
• [FIRRTL] Stop using scala for firrtl code blocks in markdown by @youngar in #3206
• [FIRRTL] Fix formatting in FIRRTLAnnotations.md by @youngar in #3207
• [FIRRTL] Use NLATable analysis to update modules in PrefixModules pass. by @prithayan in #3200
• [FIRRTL] Remove NLA verifier for circt.nonlocal on InstanceOps by @prithayan in #3208
• [FIRRTL] Update ExtractInstances pass to use NLATable analysis by @prithayan in #3172
• [FIRRTL] Remove NLA breadcrumbs from InstanceOps by @prithayan in #3176
• [HandshakeToFIRRTL] Add initial values to buffer module names by @Dinistro in #3195
• [FSM] Fix various operation builders by @mortbopet in #3209
• [FIRRTL] Update comments in NLATable header. NFC. by @prithayan in #3217
• [FIRRTL] rename mem-to-regOfVec to firrtl-mem-to-reg-of-vec by @youngar in #3205
• [MSFT] Add channel operation by @teqdruid in #3203
• [FIRRTL] Refactor NLATable analysis utilities and comments. NFC. by @prithayan in #3218
• [SVExtractTestCode][LowerToHW] Add coverage exclusion flag to testbench modules by @uenoku in #3183
• [FIRRTL] Use tap wires for GCT data taps by @fabianschuiki in #3192
• [FSM] Elaborate FSMGraph with builder capabilities by @mortbopet in #3210
• [CMake] Use CIRCT_SOURCE_DIR instead of CMAKE_SOURCE_DIR in version generation by @uenoku in #3222
• [ExportVerilog] Emit a version string only to verilog files by @uenoku in #3174
• [ExportVerilog] Add an option to print debugInfo by @uenoku in #3147
• [HWMemSimImpl] Exclude generated memory modules from coverage by @uenoku in #3224
• Add an op to constrain output statements in graph regions by @darthscsi in #3215
• [HandshakeToFIRRTL] Add initial values to buffer module names by @Dinistro in #3223
• [FIRRTL] fix cover predicate inversion by @dtzSiFive in #3219
• [FIRRTL] Dedup pass preserves the NLATable analysis. NFC. by @prithayan in #3173
• [LowerToHW] Support FIRRTL_BEFORE_INITIAL/FIRRTL_AFTER_INITIAL by @uenoku in #3193
• [FIRRTL] Fix folds of zero-width values with zero-width constants by @dtzSiFive in #3204
• [FIRRTL] Fix uses of deprecated APInt functions by @youngar in #3202

Full Changelog: circtorg-0.0.0...sifive/1/0/0

circtorg-0.0.0

This release is created to use the release tag "circtorg" as discussed in #2613.

What's Changed

• [LowerToHW] Wrap aynsc reset initiliazation by ifdef by @uenoku in #3128
• [PyCDE] Remove AppID and AppIDIndex by @teqdruid in #3124
• [FIRRTL] Use NLATable analysis for Dedup Pass by @prithayan in #3126
• [HandshakeToFIRRTL] Add support for PackOp and UnpackOp by @Dinistro in #3054
• Initial Calyx to HW conversion. by @mikeurbach in #3012
• [FIRRTL] Use NLATable analysis in LowerTypes and GrandCentral by @prithayan in #2885
• [FIRRTL] Update ModuleInliner to use NLATable analysis by @prithayan in #2903
• [HW][NFC] Rename SymbolCache -> HWSymbolCache by @mortbopet in #3136
• [HW,Support] Make symbol cache generic and move it to Support by @mortbopet in #3101
• [FIRRTL] Use NLATable analysis for EmitOMIR and LowerToHW. by @prithayan in #3140
• [FIRRTL] Composable LowerAnnotations by @seldridge in #3129
• [Docs] Fill in "Type declarations" section of HW rationale. by @mikeurbach in #3095
• [Seq] Moved pass definition to a separate header by @nandor in #3143
• [SCFToCalyx] Add special case for pipeline stages with side effects only. by @cgyurgyik in #3130
• [Handshake] Add type equality checks to InstanceOp by @Dinistro in #3151
• [Handshake] Add missing InstanceOp::getModuleType definition by @Dinistro in #3157
• [FIRRTL] Set name and file location for Comb memory wrapper module by @prithayan in #3150
• [llvm] Bump LLVM to latest main; NFC by @fabianschuiki in #3132
• [MSFT] Add an op to place all the bits in a register by @teqdruid in #3156
• Pretty print JSON metadata created by @youngar in #3158
• [SCFToCalyx] [StaticLogicToCalyx] Separate lowerings to Calyx. by @cgyurgyik in #3155
• [PyCDE] Specialize Instances by @teqdruid in #3160
• [MSFT] Teach PlacementDB about LocationVectors by @teqdruid in #3162
• [MSFT] [Python] Expose LocationVector to Python by @teqdruid in #3163
• [PyCDE] Use LocationVector to place registers by @teqdruid in #3164
• [SCFToCalyx] [StaticLogicToCalyx] Pull out while-operation interface. by @cgyurgyik in #3161
• [FIRRTL] create more strictconnect's (mkConnect -> emitConnect, enable strictconnect gen in emitConnect) by @dtzSiFive in #3045
• [HW] Relax parameter evaluation to allow resolution to passed in parameters by @trilorez in #3159
• [SCFToCalyx] [StaticLogicToCalyx] Pull out utility functions. by @cgyurgyik in #3166
• [ExportVerilog] Include Build Information in Output Files by @sinofp in #2613

Full Changelog: sifive/0/9/0...circtorg-0.0.0

Sifive Internal 0.9.0

What's Changed

• [FIRRTL] Use NLATable analysis for Dedup Pass by @prithayan in #2874
• [HW Params] Implement common factor elimination for SHR, DIV and MOD. by @DeepFlyingSky in #2958
• [llvm] Bump LLVM to latest main by @seldridge in #3107
• [MSFT] [PyCDE] Attach arbitrary RTL attributes to instances by @teqdruid in #3110
• [FIRRTL][LowerCHIRRTL] Fix enable inference for aggregates by @youngar in #3109
• [FIRRTL][AddSeqMemPorts] Don't error if there are still MemOps by @youngar in #3117
• [FIRRTL] Guard the MemToReg transformation with the annotation by @prithayan in #3118
• [HandshakeToFIRRTL] Add support for tuple types by @Dinistro in #3108
• [PrepareForEmission] Spill wires for largish expressions in concat. by @mikeurbach in #3116
• [FIRRTL] Produce pre-extract seqmem metadata by @youngar in #3123

Full Changelog: sifive/0/8/0...sifive/0/9/0