SiFive Internal Release 1.23.0

Overview

• IMDCE to eliminate dead memories
• Grand Central wire2node change
• Namehint propagation improvement
• A flag to workaround vivado BRAM inference bug
• Refactor FIRRTL canonicalizers to use ODS patterns

What's Changed

• [IMDCE] Allow dead memories to be eliminated by @nandor in #4244
• Add options for controlling emission of randomization code. by @dtzSiFive in #4240
• [FIRRTL] Cleanup GCT Views Tests to RefType, NFC by @seldridge in #4247
• [docs][Seq] Fixup seq.firreg documentation to reflect current op. by @dtzSiFive in #4250
• [FIRRTL][LowerXMR] Copy DenseMap to temporary before insertion by @prithayan in #4243
• [Docs] Fix typo in pass description by @tymcauley in #4248
• [FIRRTL][MemOp] Removed unused ports from memories by @nandor in #4242
• [SSP] Extract helper to access linked operator type, NFC. by @jopperm in #4258
• [FIRRTL][LowerXMR] Use InstanceGraph to get referencedModule by @prithayan in #4254
• [NFC] verilog-basic.mlir: Fix duplicate definition of symbol in test case. by @dtzSiFive in #4268
• Fix bug in memory canonicalizer when all ports are unused. Make patterns named to make debugging easier. by @darthscsi in #4265
• [DropNames] Reuse a droppable name attribute, nfc by @uenoku in #4259
• [LowerToHW] Fix the operand order of VectorCreateOp lowering by @uenoku in #4260
• [ExportVerilog] Fix port spacing on instances, measure emitted name. by @dtzSiFive in #4264
• Remove invalids from canonicalizers. They are always wrong. by @darthscsi in #4271
• [FIRRTL] Convert Wires To Nodes when dominance allows by @darthscsi in #4253
• [FIRRTL] Remove Annotation-style GCT Views by @seldridge in #4251
• [LowerSeqToSV] Self-assign of Async Reset FIR Reg by @seldridge in #4273
• [SV][Prepare] Improve a namehint propagation and spilling logic by @uenoku in #4261
• [Docs] Fix typo in FIRRTL Types description by @tymcauley in #4276
• Bump LLVM by @youngar in #4262
• [FIRRTL] Fix RegResetWithOneReset Canonicalizer by @seldridge in #4279
• [Handshake] Canonicalize away simple mux+cbranch structures by @RamirezLucas in #4272
• [FIRRTL] Guarantee NodeOp in GCT View by @seldridge in #4278
• [Handshake] Fix ValueRange lifetime issue. by @dtzSiFive in #4283
• [FIRRTL][Dedup] Fix cloning annotations for more context by @youngar in #4285
• Make flatten memory pass default. Create lower-memory flag. by @carlosedp in #4275
• [LowerToHW] Support 1d vector aggregate constant by @uenoku in #4280
• [Python] Register handshake passes by @teqdruid in #4290
• [RTL-SIM] Fix trace debug output in Verilator driver by @teqdruid in #4293
• [ESI] Move ESI collateral into build include directory by @teqdruid in #4292
• [SSP] Allow standalone use of OperatorLibraryOp. by @jopperm in #4222
• [ESI] Support BSPs in service metadata emission by @teqdruid in #4299
• [tools] Change tools to use CIRCT-specific bug msg by @seldridge in #4302
• [HW][Seq] Added traits to identify clocked and resettable elements by @nandor in #4294
• [FIRRTL] Add WiringProblem Solver to LowerAnnotations, use for GrandCentral Views by @seldridge in #4286
• Bump LLVM by @prithayan in #4297
• [FIRRTL] Remove Grand Central Parent Annotation by @seldridge in #4305
• [SV] Update SVExtractTestCode to handle already bound instances. by @mikeurbach in #4291
• [Seq] Use a new pass generation mechanism by @uenoku in #4304
• [SSP] Define ChainingProblem's properties. by @jopperm in #4220
• [FIRRTL] Move DShift to patterns by @darthscsi in #4308
• [CI] Swap static and shared library by @uenoku in #4310
• [FIRRTL] Preserve names on expressions when applying canonicalization patterns by @darthscsi in #4307
• [NFC] Move connect canonicalization to patterns by @darthscsi in #4306
• [FIRRTL] Eliminate more invalid canonicalization by @darthscsi in #4314
• [LowerToHW] Lower i0 operand in printf-encoded assertions to i1 by @uenoku in #4311
• [docs][NFC] Fix dead chisel-lang API links "temporarily". by @dtzSiFive in #4313
• [FIRRTL] Move more canonicalizations to patterns. by @darthscsi in #4316
• [FIRRTL] Change Wires to Nodes in WiringProblems by @seldridge in #4312
• Revert "[FIRRTL] Convert Wires To Nodes when dominance allows (#4253)" by @uenoku in #4317
• [LowerAnnotations][WiringProblem] minor reorg, debug print all problems. by @dtzSiFive in #4322
• [GrandCentralTaps] Move (new) MemTaps to WiringProblem. by @dtzSiFive in #4320
• [Docs] Add SSP to dialect diagram. by @jopperm in #4295
• [SV] Verify that sv.interface.instance ops have a nonempty name by @rwy7 in #4315
• [HWMemSim, LowerSeqToSV] Add a flag to annotate array registers with (*ram_style = "distributed" *) by @uenoku in #4288
• [FIRRTL] Require MultibitMuxOp Index is Unsigned by @seldridge in #4325
• [FIRRTL][CheckCombCycles] Detect input port self loops by @prithayan in #4330
• [Handshake][lit] Move buff insertion tests to correct dir by @Dinistro in #4329
• llvm-bump by @Ramlakshmi3733 in #4321

New Contributors

• @RamirezLucas made their first contribution in #4272
• @carlosedp made their first contribution in #4275
• @rwy7 made their first contribution in #4315
• @Ramlakshmi3733 made their first contribution in #4321

Full Changelog: sifive/1/22/0...sifive/1/23/0

SiFive Internal Release 1.22.1

What's Changed

• Backport changes to sifive-1.22 by @mikeurbach in #4287

Full Changelog: sifive/1/22/0...sifive/1/22/1

SiFive Internal Release 1.22.0

What's Changed

• Fix GCT View Directory Behavior for DUT
• Significantly improve performance of Grand Central Taps
• [GrandCentral] Get the correct Subinterface name
• Fix DontTouch annotation handling in Dedup
• Add folds for aggregate constants and subaccesses
• Legalize keywords by per-basename uniqification

Full Changelog: sifive/1/21/0...sifive/1/22/0

SiFive Internal Release 1.21.0

What's Changed

• Limit useless locs in dedup, improving performance when deduplicating many modules
• Ignore TestBenchDirAnno if no DUT in BlackBoxReader
• Improvements to location information for if and else statements
• Fix missing paren for clog2 when nested
• Fix double parens when adding $signed() around an operand
• Change lowering-options command line option, wireSpillingHeuristic=spillAllMux is now disallowMuxInlining
• Handle Unknown source widths in GrandCentralTaps
• Remove mux pragmas when memory size is 1
• Improved array concatenation canonicalizers
• Fix GCT output dir for mod/extmod
• Further deduplication performance improvements

Full Changelog: sifive/1/20/0...sifive/1/21/0

SiFive Internal Release 1.20.0

Overview

• Added folders for constant clock and constant reset registers, enabled by recent FIRRTL spec clarifications of undefined behavior
• Optimizations around how array ops are emitted
• Fixes for the new module inlining and instance extraction in ExtractTestCode
• Fixes for Windows compilation
• Optimization in CheckCombCycles to save >35% runtime for that pass in some designs
• Added the TraceNames pass to implement Chisel's Trace API

What's Changed

• [Seq] Add const-clock and const-reset folders for FirRegOp by @fabianschuiki in #4090
• [FIRRTL][ExpandWhens] Add iterator to HashTableStack by @youngar in #4096
• [LowerToHW] Lower source subindex into array_get instead of read_inout and array_index by @uenoku in #4067
• [SV] Fix SVExtractTestCode to handle inlining cycles. by @mikeurbach in #4092
• [SV] Fix SVExtractTestCode to extract all results of instances. by @mikeurbach in #4101
• [SV] Fix SVExtractTestCode to not duplicate when inlining. by @mikeurbach in #4106
• [HW] Canonicalized array create to slices by @nandor in #4114
• [comb] Build Reduction Ops whenever possible by @Schottkyc137 in #3394
• [FIRRTL][CheckCombCycles] Use special class for End Iterator by @prithayan in #4086
• [FIRRTL] Add TraceNames Pass to Implement Chisel's Trace API by @seldridge in #4065

Full Changelog: sifive/1/19/0...sifive/1/20/0

SiFive Internal Release 1.19.0

What's Changed

• [ExportVerilog] Remove old emission code by @uenoku in #4079
• Fixes to build system to support unittests again, add to CI by @dtzSiFive in #4082
• [FSMToSV] Erase typescope if empty by @mortbopet in #4093
• [SV] Add feature flags to new SVExtractTestCode features. by @mikeurbach in #4094

Full Changelog: sifive/1/18/0...sifive/1/19/0

SiFive Internal Release 1.18.0

Overview

• Unifies lowering options related to spilling large constructs into wires
• Unifies cleanup code in SVExtractTestCode to avoid use-after-free or double free

Otherwise, this is a minor update on top of https://github.com/llvm/circt/releases/tag/sifive%2F1%2F17%2F0

What's Changed

• [HWMemSimImpl, LowerToHW] Add mux pragmas to memory reads and add a flag to control mux pragmas by @uenoku in #3913
• [SV] Fix potential to erase ops multiple times in SVExtractTestCode. by @mikeurbach in #4085
• [PrepareForEmission, LoweringOptions] Unify LoweringOptions regarding term sizes into maximumNumberOfTermsPerExpression by @uenoku in #4078

Full Changelog: sifive/1/17/0...sifive/1/18/0

SiFive Internal Release 1.17.0

Overview

• Improvements to HW canonicalizers and ExportVerilog
• New wire spilling heuristics in PrepareForEmission
• RefType and RefOp improvements
• Enhanced SVExtractTestCode to extract some instances and inline modules that just wrap extracted test code
• Performance improvement in verifier

What's Changed

• [FIRRTL][CheckCombCycles] Ignore register self initialization connects by @prithayan in #3965
• Revert "[FIRRTL] Verify FModuleLike's have unique port names." by @dtzSiFive in #3976
• [PrepareForEmission] Fix UAF by @uenoku in #3984
• [FIRRTL] Reuse HierPathOp's when creating in LA, fix GC(T) cleanup, add SymbolDCE to pipeline by @dtzSiFive in #3979
• [SV] Erase empty if-else block by @uenoku in #3988
• [FIRRTL][LowerTypes] Lower aggregate type operand by @prithayan in #3982
• [PrepareForEmission] Perform wire spilling based estimated expression size by @uenoku in #3752
• [FIRRTL][RefType] Add a new RefSub Op by @prithayan in #3993
• [FIRRTL][LowerXMR] Lower RefSubOp to memory XMR by @prithayan in #3994
• [ExportVerilog] Improve XMR emission when used as bound inputs by @uenoku in #3995
• [FIRRTL][RefType] Lower RefType in LowerTypes by @prithayan in #3990
• [HW] Enable i0 for HWIntegerType by @mortbopet in #3985
• [FIRRTL][LowerAnnotation] Mark the DataTap sink as NoDedup by @prithayan in #4005
• [FIRRTL][GrandCentral] Update attribute wireName to sink by @prithayan in #4006
• [HW] Add hw.struct_explode canonicalizer by @mortbopet in #4010
• [HW] Add PruneZeroValuedLogic to PrepareForEmission by @mortbopet in #3935
• [FIRRTL] Fix GCT Instance Name Prefix by @seldridge in #4016
• [FIRRTL][GrandCentral] Revert MemTap sink to array attribute by @prithayan in #4022
• [FIRRTL] Allow foreign types in module/instance ports by @fabianschuiki in #2694
• [ExportVerilog] emit comments on else and endif for readability by @dtzSiFive in #4024
• [SV] Update ExtractTestCode to extract input only modules. by @mikeurbach in #4014
• [FIRRTL][InferWidths] Exclude foreign types, add conversion cast support by @fabianschuiki in #4026
• [FIRRTL][LowerTypes] Pass through foreign types in lowerProducer by @fabianschuiki in #4027
• [FIRRTL][InferResets] Don't abort on foreign types by @fabianschuiki in #4025
• [ExportVerilog] Improve error message for emitting unsupported ops by @mortbopet in #4011
• [HW] Improve asm result names for struct extract, explode ops by @mortbopet in #3998
• [ExportVerilog] Handle hw.struct_explode by @mortbopet in #4012
• [PrepareForEmission] Improve namehints heuristic and add mux heuristic by @uenoku in #4019
• [PrettifyVerilog] Fix a crash caused by comparing different width of APInt by @uenoku in #4031
• [ExportVerilog][NFC] Remove blockDeclaration* tracking as unused. by @dtzSiFive in #4046
• [ExportVerilog][NFC] Drop another unused tracking cursor. by @dtzSiFive in #4049
• [HW] Add a folder for array slice op by @uenoku in #4052
• Don't read lowering options from hidden global options by @darthscsi in #4038
• [SV] Allow packed arrays for index part select inout by @uenoku in #4051
• [FIRParser] Stop double deserializing OMIR annos by @youngar in #4062
• [FIRRTL][Dedup] Update few error messages by @prithayan in #4037
• [ExportVerilog] Fix use of wrong decl alignment after emitting a block. by @dtzSiFive in #4054
• [FIRRTL] Implement out-of-bounds as array extension by @darthscsi in #4069
• [HW] Add a folder for a constant array created by a bitcast by @uenoku in #4066
• [ExtractTestCode] Support extracting instances in some cases. by @mikeurbach in #3522
• [NFC] Cache sybmol lookup removing O(N^2) behavior from CircuitOp::verify by @darthscsi in #4077
• [SV] Update ExtractTestCode to inline input only modules. by @mikeurbach in #4063
• [Seq] Add FirReg no-update canonicalizer by @youngar in #4060
• [SV] Fix heap-use-after-free in recent SVExtractTestCode change. by @mikeurbach

Full Changelog: sifive/1/16/0...sifive/1/17/0

SiFive Internal Release 1.16.0

What's Changed

• Lower muxes feeding registers to ifs
• Support GrandCentral internalPath on Modules
• Allow GrandCentral source and companion modules to be further apart in the hierarchy
• Improvements to aggregate preservation towards lowering 1-dimensional vector to Verilog
• Add canonicalizer to simplify an array where all elements are identical

New Contributors

• @jackkoenig made their first contribution in #3829

Full Changelog: sifive/1/15/0...sifive/1/16/0

SiFive Internal Release 1.5.3

What's Changed

• Backport: [FIRRTL][SV] Add comment attribute to GC interfaces and modules by @youngar in #3923

Full Changelog: sifive/1/5/2...sifive/1/5/3