Polara ASIC Chip Bring Up Merge #5
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…e-v-polara-apu into openpiton_polara_fpga
…oard genesys2 --design chipset --core ariane --jobs 32.
…n to test Polara in loopback.
…core-v-polara-apu into genesys2_chipset_target
…t which is the asic's input port.
…e sends packets on.
…core-v-polara-apu into genesys2_chipset_target
…nchronized one. Added go signal to control when data is sent.
…ing on the other in fpga bridge. Constraints updated for ILA.
…with it. The ILA failed timing
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This pull request includes the work done from May-December 2024 which focused on implementing a chipset on the Genesys 2 FPGA board to test the Polara ASIC. More information is included in the attached pdf.
2024_12_18_pull_request.pdf