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Merge pull request #901 from bohdan-tymkiv/psoc64-support
Add support for new revisions of secure PSoC64 devices
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,167 @@ | ||
| # pyOCD debugger | ||
| # Copyright (c) 2020 Cypress Semiconductor Corporation | ||
| # SPDX-License-Identifier: Apache-2.0 | ||
| # | ||
| # Licensed under the Apache License, Version 2.0 (the "License"); | ||
| # you may not use this file except in compliance with the License. | ||
| # You may obtain a copy of the License at | ||
| # | ||
| # http://www.apache.org/licenses/LICENSE-2.0 | ||
| # | ||
| # Unless required by applicable law or agreed to in writing, software | ||
| # distributed under the License is distributed on an "AS IS" BASIS, | ||
| # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
| # See the License for the specific language governing permissions and | ||
| # limitations under the License. | ||
|
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| import logging | ||
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| from .component import CoreSightCoreComponent | ||
| from ..core.target import Target | ||
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| LOG = logging.getLogger(__name__) | ||
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| DEAD_VALUE = 0 | ||
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| class GenericMemAPTarget(Target, CoreSightCoreComponent): | ||
| """! @brief This target represents ARM debug Access Port without a CPU | ||
| It may be used to access the address space of the target via Access Ports | ||
| without real ARM CPU core behind it. For instance Cypress PSoC64 devices have | ||
| three APs implemented in the hardware: | ||
| * AP #0 -> CPU-less AHB AP | ||
| * AP #1 -> Cortex-M0+ AP | ||
| * AP #2 -> Cortex-M4F AP | ||
| Depending on the protection state, AP #1 and AP #2 can be permanently disabled. | ||
| This class allows to communicate with Secure FW running on the target via AP #0. | ||
| Most of the methods in this class (except memory access methods) are empty/dummy. | ||
| """ | ||
|
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| def __init__(self, session, ap, memory_map=None, core_num=0, cmpid=None, address=None): | ||
| Target.__init__(self, session, memory_map) | ||
| CoreSightCoreComponent.__init__(self, ap, cmpid, address) | ||
| self.core_number = core_num | ||
| self.core_type = DEAD_VALUE | ||
| self._target_context = None | ||
| self.register_list = [] | ||
|
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| def add_child(self, cmp): | ||
| pass | ||
|
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| @property | ||
| def supported_security_states(self): | ||
| return Target.SecurityState.NONSECURE, | ||
|
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| def init(self): | ||
| pass | ||
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| def disconnect(self, resume=True): | ||
| pass | ||
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| def write_memory(self, addr, value, transfer_size=32): | ||
| self.ap.write_memory(addr, value, transfer_size) | ||
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| def read_memory(self, addr, transfer_size=32, now=True): | ||
| return self.ap.read_memory(addr, transfer_size, True) | ||
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| def read_memory_block8(self, addr, size): | ||
| return self.ap.read_memory_block8(addr, size) | ||
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| def write_memory_block8(self, addr, data): | ||
| self.ap.write_memory_block8(addr, data) | ||
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| def write_memory_block32(self, addr, data): | ||
| self.ap.write_memory_block32(addr, data) | ||
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| def read_memory_block32(self, addr, size): | ||
| return self.ap.read_memory_block32(addr, size) | ||
|
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| def halt(self): | ||
| pass | ||
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| def step(self, disable_interrupts=True, start=0, end=0): | ||
| pass | ||
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| def reset(self, reset_type=None): | ||
| pass | ||
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| def reset_and_halt(self, reset_type=None): | ||
| self.reset(reset_type) | ||
| pass | ||
|
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| def get_state(self): | ||
| return Target.State.HALTED | ||
|
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| def get_security_state(self): | ||
| return Target.SecurityState.NONSECURE | ||
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| def is_running(self): | ||
| return self.get_state() == Target.State.RUNNING | ||
|
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| def is_halted(self): | ||
| return self.get_state() == Target.State.HALTED | ||
|
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| def resume(self): | ||
| pass | ||
|
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| def find_breakpoint(self, addr): | ||
| return None | ||
|
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| def read_core_register(self, reg): | ||
| return DEAD_VALUE | ||
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| def read_core_register_raw(self, reg): | ||
| return DEAD_VALUE | ||
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| def read_core_registers_raw(self, reg_list): | ||
| return [DEAD_VALUE] * len(reg_list) | ||
|
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| def write_core_register(self, reg, data): | ||
| pass | ||
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| def write_core_register_raw(self, reg, data): | ||
| pass | ||
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| def write_core_registers_raw(self, reg_list, data_list): | ||
| pass | ||
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| def set_breakpoint(self, addr, type=Target.BreakpointType.AUTO): | ||
| return False | ||
|
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| def remove_breakpoint(self, addr): | ||
| pass | ||
|
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| def get_breakpoint_type(self, addr): | ||
| return None | ||
|
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| def set_watchpoint(self, addr, size, type): | ||
| return False | ||
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| def remove_watchpoint(self, addr, size, type): | ||
| pass | ||
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| def set_vector_catch(self, enable_mask): | ||
| pass | ||
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| def get_vector_catch(self): | ||
| return 0 | ||
|
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| def get_target_xml(self): | ||
| return None | ||
|
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| def get_halt_reason(self): | ||
| return Target.HaltReason.DEBUG | ||
|
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| def get_target_context(self, core=None): | ||
| return self._target_context | ||
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| def set_target_context(self, context): | ||
| self._target_context = context | ||
|
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| def create_init_sequence(self): | ||
| pass | ||
|
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| def mass_erase(self): | ||
| pass |
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