Implement cs0 and cs1 as logic equations, not muxes

Signed-off-by: Joachim Strömbergson <[email protected]>
tillitis · Mar 18, 2024 · ab8ca02 · ab8ca02
1 parent f735fae
commit ab8ca02
Showing 1 changed file with 2 additions and 4 deletions.
diff --git a/hw/application_fpga/rtl/ram.v b/hw/application_fpga/rtl/ram.v
@@ -125,14 +125,12 @@ module ram(
   //----------------------------------------------------------------
   always @*
     begin : mem_mux
-      cs0 = 1'h0;
-      cs1 = 1'h0;
+      cs0 = ~address[14] & cs;
+      cs1 = address[14] & cs;
 
       if (address[14]) begin
-        cs1             = cs;
         muxed_read_data = read_data1;
       end else begin
-        cs0             = cs;
         muxed_read_data = read_data0;
       end
     end