snippets: add ram-console snippet support

The ram-console snippet disabled UART console and enabled the RAM console with the option link the RAM console buffer to a dedicate section in a new added memory-region. Signed-off-by: Hou Zhiqiang <[email protected]>
zephyrproject-rtos · Jun 12, 2024 · fd584b4 · fd584b4
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diff --git a/snippets/ram-console/README.rst b/snippets/ram-console/README.rst
@@ -0,0 +1,37 @@
+.. _snippet-ram-console:
+
+RAM Console Snippet (ram-console)
+#################################
+
+.. code-block:: console
+
+   west build -S ram-console [...]
+
+Overview
+********
+
+This snippet redirects console output to a RAM buffer. The RAM console
+buffer is a global array located in RAM region by default, whose address
+is unknown before building. The RAM console driver also supports using
+a dedicated section for the RAM console buffer with prefined address.
+
+How to enable RAM console buffer section
+****************************************
+
+Add board dts overlay to this snippet to add property ``zephyr,ram-console``
+in the chosen node and memory-region node with compatible string
+:dtcompatible:`zephyr,memory-region` as the following:
+
+.. code-block:: DTS
+
+    / {
+        chosen {
+            zephyr,ram-console = &snippet_ram_console;
+        };
+
+       snippet_ram_console: memory@93d00000 {
+            compatible = "zephyr,memory-region";
+            reg = <0x93d00000 DT_SIZE_K(4)>;
+            zephyr,memory-region = "RAM_CONSOLE";
+       };
+    };
diff --git a/snippets/ram-console/boards/imx8mm_evk_mimx8mm6_a53.overlay b/snippets/ram-console/boards/imx8mm_evk_mimx8mm6_a53.overlay
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		zephyr,ram-console = &snippet_ram_console;
+	};
+
+	snippet_ram_console: memory@93d00000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x93d00000 DT_SIZE_K(4)>;
+		zephyr,memory-region = "RAM_CONSOLE";
+	};
+};
diff --git a/snippets/ram-console/boards/imx8mn_evk_mimx8mn6_a53.overlay b/snippets/ram-console/boards/imx8mn_evk_mimx8mn6_a53.overlay
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		zephyr,ram-console = &snippet_ram_console;
+	};
+
+	snippet_ram_console: memory@93d00000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x93d00000 DT_SIZE_K(4)>;
+		zephyr,memory-region = "RAM_CONSOLE";
+	};
+};
diff --git a/snippets/ram-console/boards/imx8mp_evk_mimx8ml8_a53.overlay b/snippets/ram-console/boards/imx8mp_evk_mimx8ml8_a53.overlay
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		zephyr,ram-console = &snippet_ram_console;
+	};
+
+	snippet_ram_console: memory@c0100000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xc0100000 DT_SIZE_K(4)>;
+		zephyr,memory-region = "RAM_CONSOLE";
+	};
+};
diff --git a/snippets/ram-console/boards/imx93_evk_mimx9352_a55.overlay b/snippets/ram-console/boards/imx93_evk_mimx9352_a55.overlay
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		zephyr,ram-console = &snippet_ram_console;
+	};
+
+	snippet_ram_console: memory@d0100000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xd0100000 DT_SIZE_K(4)>;
+		zephyr,memory-region = "RAM_CONSOLE";
+	};
+};
diff --git a/snippets/ram-console/ram-console.conf b/snippets/ram-console/ram-console.conf
@@ -0,0 +1,9 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Disable UART Console
+CONFIG_UART_CONSOLE=n
+# Enable RAM Console
+CONFIG_RAM_CONSOLE=y
diff --git a/snippets/ram-console/snippet.yml b/snippets/ram-console/snippet.yml
@@ -0,0 +1,32 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+name: ram-console
+append:
+  EXTRA_CONF_FILE: ram-console.conf
+
+boards:
+  imx8mm_evk/mimx8mm6/a53:
+    append:
+      EXTRA_DTC_OVERLAY_FILE: boards/imx8mm_evk_mimx8mm6_a53.overlay
+  imx8mm_evk/mimx8mm6/a53/smp:
+    append:
+      EXTRA_DTC_OVERLAY_FILE: boards/imx8mm_evk_mimx8mm6_a53.overlay
+  imx8mn_evk/mimx8mn6/a53:
+    append:
+      EXTRA_DTC_OVERLAY_FILE: boards/imx8mn_evk_mimx8mn6_a53.overlay
+  imx8mn_evk/mimx8mn6/a53/smp:
+    append:
+      EXTRA_DTC_OVERLAY_FILE: boards/imx8mn_evk_mimx8mn6_a53.overlay
+  imx8mp_evk/mimx8ml8/a53:
+    append:
+      EXTRA_DTC_OVERLAY_FILE: boards/imx8mp_evk_mimx8ml8_a53.overlay
+  imx8mp_evk/mimx8ml8/a53/smp:
+    append:
+      EXTRA_DTC_OVERLAY_FILE: boards/imx8mp_evk_mimx8ml8_a53.overlay
+  imx93_evk/mimx9352/a55:
+    append:
+      EXTRA_DTC_OVERLAY_FILE: boards/imx93_evk_mimx9352_a55.overlay