soc: nxp_mxrt7xx: Fix cache implementation for CPU0 #85541
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The following west manifest projects have changed revision in this Pull Request:
✅ All manifest checks OK Note: This message is automatically posted and updated by the Manifest GitHub Action. |
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This SoC has an external XCACHE controller for CPU0 instruction and data bus. Add code to enable the data cache. Instruction cache is already enabled by SystemInit. Signed-off-by: Mahesh Mahadevan <[email protected]>
Update the HAL driver used for RT700 Cache Signed-off-by: Mahesh Mahadevan <[email protected]>
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This SoC has an external XCACHE controller for CPU0 instruction and data bus. Add code to enable the data cache. Instruction cache is already enabled by SystemInit.