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[AIE2P] Extend AIESubRegConstrainer for FIFO ops
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Covering also *InstrInfo required changes.
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andcarminati committed Jan 20, 2025
1 parent 0432528 commit 070c32b
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Showing 15 changed files with 771 additions and 435 deletions.
58 changes: 29 additions & 29 deletions llvm/lib/Target/AIE/AIE2InstrInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
// (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
// (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
//
//===----------------------------------------------------------------------===//
//
Expand Down Expand Up @@ -1207,8 +1207,8 @@ AIE2InstrInfo::getTiedRegInfo(unsigned Opcode) const {
// Constraints = "$count_out=$mod.sub_dim_count"
return {TiedRegOperands{
/*DstOps=*/{{/*OpIdx=*/2, /*SubRegIdx=*/AIE2::sub_dim_count}},
/*SrcOp=*/{/*OpIdx=*/4, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}};
/*SrcOp=*/{{/*OpIdx=*/4, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}}};
case AIE2::LDA_3D_dmv_lda_q:
case AIE2::LDA_3D_dms_lda:
case AIE2::LDA_3D_S8_dmhb_lda:
Expand All @@ -1231,8 +1231,8 @@ AIE2InstrInfo::getTiedRegInfo(unsigned Opcode) const {
/*DstOps=*/{
{/*OpIdx=*/2, /*SubRegIdx=*/AIE2::sub_dim_count},
{/*OpIdx=*/3, /*SubRegIdx=*/AIE2::sub_hi_dim_then_sub_dim_count}},
/*SrcOp=*/{/*OpIdx=*/5, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}};
/*SrcOp=*/{{/*OpIdx=*/5, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}}};
case AIE2::VLDA_2D_UPS_S32_D16:
case AIE2::VLDA_2D_UPS_S64_D32:
case AIE2::VLDA_2D_UPS_S32_D8:
Expand All @@ -1244,8 +1244,8 @@ AIE2InstrInfo::getTiedRegInfo(unsigned Opcode) const {
// Constraints = "$count_out=$mod.sub_dim_count"
return {TiedRegOperands{
/*DstOps=*/{{/*OpIdx=*/2, /*SubRegIdx=*/AIE2::sub_dim_count}},
/*SrcOp=*/{/*OpIdx=*/5, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}};
/*SrcOp=*/{{/*OpIdx=*/5, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}}};
case AIE2::VLDA_3D_UPS_S32_D16:
case AIE2::VLDA_3D_UPS_S64_D32:
case AIE2::VLDA_3D_UPS_S32_D8:
Expand All @@ -1260,8 +1260,8 @@ AIE2InstrInfo::getTiedRegInfo(unsigned Opcode) const {
/*DstOps=*/{
{/*OpIdx=*/2, /*SubRegIdx=*/AIE2::sub_dim_count},
{/*OpIdx=*/3, /*SubRegIdx=*/AIE2::sub_hi_dim_then_sub_dim_count}},
/*SrcOp=*/{/*OpIdx=*/6, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}};
/*SrcOp=*/{{/*OpIdx=*/6, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}}};
case AIE2::ST_2D_dmv_sts_q:
case AIE2::VST_2D_dmw_sts_am:
case AIE2::VST_2D_dmw_sts_w:
Expand All @@ -1272,17 +1272,17 @@ AIE2InstrInfo::getTiedRegInfo(unsigned Opcode) const {
// Constraints = "$count_out=$mod.sub_dim_count"
return {TiedRegOperands{
/*DstOps=*/{{/*OpIdx=*/1, /*SubRegIdx=*/AIE2::sub_dim_count}},
/*SrcOp=*/{/*OpIdx=*/4, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}};
/*SrcOp=*/{{/*OpIdx=*/4, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}}};
case AIE2::VST_2D_PACK_D4_D8:
case AIE2::VST_2D_PACK_D8_D16:
case AIE2::VST_2D_PACK_S4_S8:
case AIE2::VST_2D_PACK_S8_S16:
// Constraints = "$count_out=$mod.sub_dim_count"
return {TiedRegOperands{
/*DstOps=*/{{/*OpIdx=*/1, /*SubRegIdx=*/AIE2::sub_dim_count}},
/*SrcOp=*/{/*OpIdx=*/3, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}};
/*SrcOp=*/{{/*OpIdx=*/3, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}}};
case AIE2::ST_3D_dmv_sts_q:
case AIE2::VST_3D_dmw_sts_w:
case AIE2::VST_3D_128:
Expand All @@ -1296,8 +1296,8 @@ AIE2InstrInfo::getTiedRegInfo(unsigned Opcode) const {
/*DstOps=*/{
{/*OpIdx=*/1, /*SubRegIdx=*/AIE2::sub_dim_count},
{/*OpIdx=*/2, /*SubRegIdx=*/AIE2::sub_hi_dim_then_sub_dim_count}},
/*SrcOp=*/{/*OpIdx=*/5, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}};
/*SrcOp=*/{{/*OpIdx=*/5, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}}};
case AIE2::VST_3D_PACK_D4_D8:
case AIE2::VST_3D_PACK_D8_D16:
case AIE2::VST_3D_PACK_S4_S8:
Expand All @@ -1308,23 +1308,23 @@ AIE2InstrInfo::getTiedRegInfo(unsigned Opcode) const {
/*DstOps=*/{
{/*OpIdx=*/1, /*SubRegIdx=*/AIE2::sub_dim_count},
{/*OpIdx=*/2, /*SubRegIdx=*/AIE2::sub_hi_dim_then_sub_dim_count}},
/*SrcOp=*/{/*OpIdx=*/4, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}};
/*SrcOp=*/{{/*OpIdx=*/4, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}}};
case AIE2::VST_CONV_2D_BF16_FP32:
// Constraints = "$count_out=$mod.sub_dim_count"
return {TiedRegOperands{
/*DstOps=*/{{/*OpIdx=*/1, /*SubRegIdx=*/AIE2::sub_dim_count}},
/*SrcOp=*/{/*OpIdx=*/3, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}};
/*SrcOp=*/{{/*OpIdx=*/3, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}}};
case AIE2::VST_CONV_3D_BF16_FP32:
// Constraints = "$count_lo_out=$mod.sub_dim_count,
// $count_hi_out=$mod.sub_hi_dim_then_sub_dim_count"
return {TiedRegOperands{
/*DstOps=*/{
{/*OpIdx=*/1, /*SubRegIdx=*/AIE2::sub_dim_count},
{/*OpIdx=*/2, /*SubRegIdx=*/AIE2::sub_hi_dim_then_sub_dim_count}},
/*SrcOp=*/{/*OpIdx=*/4, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}};
/*SrcOp=*/{{/*OpIdx=*/4, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}}};
case AIE2::VST_2D_SRS_D8_S32:
case AIE2::VST_2D_SRS_D16_S64:
case AIE2::VST_2D_SRS_D16_S32:
Expand All @@ -1336,8 +1336,8 @@ AIE2InstrInfo::getTiedRegInfo(unsigned Opcode) const {
// Constraints = "$count_out=$mod.sub_dim_count"
return {TiedRegOperands{
/*DstOps=*/{{/*OpIdx=*/1, /*SubRegIdx=*/AIE2::sub_dim_count}},
/*SrcOp=*/{/*OpIdx=*/3, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}};
/*SrcOp=*/{{/*OpIdx=*/3, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}}};
case AIE2::VST_3D_SRS_D8_S32:
case AIE2::VST_3D_SRS_D16_S64:
case AIE2::VST_3D_SRS_D16_S32:
Expand All @@ -1352,17 +1352,17 @@ AIE2InstrInfo::getTiedRegInfo(unsigned Opcode) const {
/*DstOps=*/{
{/*OpIdx=*/1, /*SubRegIdx=*/AIE2::sub_dim_count},
{/*OpIdx=*/2, /*SubRegIdx=*/AIE2::sub_hi_dim_then_sub_dim_count}},
/*SrcOp=*/{/*OpIdx=*/4, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}};
/*SrcOp=*/{{/*OpIdx=*/4, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}}};
case AIE2::PADDA_2D:
case AIE2::PADDB_2D:
case AIE2::PADDS_2D:
// Constraints = "$count_out=$mod.sub_dim_count"
return {TiedRegOperands{
/*DstOps=*/{{/*OpIdx=*/1, /*SubRegIdx=*/AIE2::sub_dim_count}},
/*SrcOp=*/
{/*OpIdx=*/3, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}};
{{/*OpIdx=*/3, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}}};
case AIE2::PADDA_3D:
case AIE2::PADDB_3D:
case AIE2::PADDS_3D:
Expand All @@ -1373,8 +1373,8 @@ AIE2InstrInfo::getTiedRegInfo(unsigned Opcode) const {
{/*OpIdx=*/1, /*SubRegIdx=*/AIE2::sub_dim_count},
{/*OpIdx=*/2, /*SubRegIdx=*/AIE2::sub_hi_dim_then_sub_dim_count}},
/*SrcOp=*/
{/*OpIdx=*/4, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}};
{{/*OpIdx=*/4, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}}};
default:
return {};
}
Expand Down
29 changes: 23 additions & 6 deletions llvm/lib/Target/AIE/AIEBaseInstrInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
// (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
// (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
//
//===----------------------------------------------------------------------===//
//
Expand Down Expand Up @@ -775,12 +775,29 @@ bool AIEBaseInstrInfo::verifyTiedRegisters(const MachineInstr &MI,
};

for (const TiedRegOperands &Regs : getTiedRegInfo(MI)) {
const MachineOperand &SrcOp = MI.getOperand(Regs.SrcOp.OpIdx);
if (!VerifyTiedReg(SrcOp, SrcOp, Regs.SrcOp.SubRegIdx))
return false;
for (const OperandSubRegMapping &DstOp : Regs.DstOps) {
if (!VerifyTiedReg(MI.getOperand(DstOp.OpIdx), SrcOp, DstOp.SubRegIdx))
if (Regs.SrcOps.size() == 1) {
auto NoSubRegSrcOp = Regs.SrcOps.front();
const MachineOperand &SrcOp = MI.getOperand(NoSubRegSrcOp.OpIdx);
if (!VerifyTiedReg(SrcOp, SrcOp, NoSubRegSrcOp.SubRegIdx)) {
ErrInfo = "Tied physical registers must match";
return false;
}
for (const OperandSubRegMapping &DstOp : Regs.DstOps) {
if (!VerifyTiedReg(MI.getOperand(DstOp.OpIdx), SrcOp,
DstOp.SubRegIdx)) {
ErrInfo = "Tied physical registers must match";
return false;
}
}
} else {
assert(Regs.DstOps.size() == Regs.SrcOps.size());
for (unsigned TiedNum = 0; TiedNum < Regs.DstOps.size(); TiedNum++) {
if (!VerifyTiedReg(MI.getOperand(Regs.SrcOps[TiedNum].OpIdx),
MI.getOperand(Regs.DstOps[TiedNum].OpIdx), 0)) {
ErrInfo = "Tied physical registers must match";
return false;
}
}
}
}
return true;
Expand Down
4 changes: 3 additions & 1 deletion llvm/lib/Target/AIE/AIEBaseInstrInfo.h
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
// (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
// (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
//
//===----------------------------------------------------------------------===//
//
Expand Down Expand Up @@ -299,6 +299,8 @@ struct AIEBaseInstrInfo : public TargetInstrInfo {
return getTiedRegInfo(MI.getOpcode());
}

virtual bool hasTiedRegInfo(MachineInstr &I) const { return false; }

/// Finds the opcode that is equivalent to \p Opcode except some operands
/// are expanded into multiple sub-registers operands to facilitate register
/// allocation.
Expand Down
97 changes: 67 additions & 30 deletions llvm/lib/Target/AIE/AIESubRegConstrainer.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -4,13 +4,12 @@
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
// (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
// (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
//
//===----------------------------------------------------------------------===//

#include "AIEBaseInstrInfo.h"
#include "AIETiedRegOperands.h"

#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/Passes.h"
Expand Down Expand Up @@ -70,12 +69,14 @@ bool AIESubRegConstrainer::runOnMachineFunction(MachineFunction &MF) {
void AIESubRegConstrainer::replaceRegOperands(Register OldReg, Register NewReg,
unsigned NewSubReg,
MachineRegisterInfo &MRI) {

const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
assert(MRI.hasOneDef(OldReg) && "OldReg expected to be in SSA form.");

for (MachineOperand &Op : make_early_inc_range(MRI.reg_operands(OldReg))) {
Op.setReg(NewReg);

// Compose the sub-register index if the dst operand already has
// subregisters
// TODO: We could compose sub-registers, but that's not needed at this point
// because AIE2's DC registers have no sub-registers.
if (Op.getSubReg())
Op.setSubReg(TRI.composeSubRegIndices(NewSubReg, Op.getSubReg()));
else
Expand All @@ -91,55 +92,91 @@ void AIESubRegConstrainer::replaceRegOperands(Register OldReg, Register NewReg,
}
}

static bool isTiedPair(const MachineInstr &MI,
const OperandSubRegMapping &DstOp,
const OperandSubRegMapping &SrcOp) {
if (MI.getOperand(DstOp.OpIdx).getReg() ==
MI.getOperand(SrcOp.OpIdx).getReg()) {
assert(MI.getOperand(DstOp.OpIdx).getSubReg() == DstOp.SubRegIdx &&
MI.getOperand(SrcOp.OpIdx).getSubReg() == SrcOp.SubRegIdx);
static bool isTiedPair(const MachineInstr &MI, const OperandSubRegMapping &Op1,
const OperandSubRegMapping &Op2) {
if (&Op1 == &Op2)
return true;
if (MI.getOperand(Op1.OpIdx).getReg() == MI.getOperand(Op2.OpIdx).getReg()) {
assert(MI.getOperand(Op1.OpIdx).getSubReg() == Op1.SubRegIdx &&
MI.getOperand(Op2.OpIdx).getSubReg() == Op2.SubRegIdx);
return true;
}
return false;
}

void AIESubRegConstrainer::processTiedOperands(const TiedRegOperands &Regs,
MachineInstr &MI) {
assert(!MI.getOperand(Regs.SrcOp.OpIdx).getSubReg() && !Regs.SrcOp.SubRegIdx);
assert(Regs.SrcOps.size() >= 1);
MachineFunction &MF = *MI.getParent()->getParent();
auto *TII = MF.getSubtarget().getInstrInfo();
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
MachineRegisterInfo &MRI = MF.getRegInfo();

if (all_of(Regs.DstOps, [&Regs, &MI](const OperandSubRegMapping &DstOp) {
return isTiedPair(MI, DstOp, Regs.SrcOp);
})) {
auto AreOperandsTied =
[&Regs, &MI](const SmallVector<OperandSubRegMapping, 4> &Ops) {
return all_of(Ops, [&](const OperandSubRegMapping &DstOp) {
return isTiedPair(MI, DstOp, Regs.SrcOps.front());
});
};

if (AreOperandsTied(Regs.SrcOps) && AreOperandsTied(Regs.DstOps)) {
// Nothing to do if all registers are already tied.
return;
}

// Create a new virtual register which will be used to replace all the uses
// of tied destination registers, and the use of SrcReg in MI.
auto SrcReg = MI.getOperand(Regs.SrcOp.OpIdx).getReg();
auto CopyReg = MRI.createVirtualRegister(MRI.getRegClass(SrcReg));
const TargetRegisterClass *SuperRegRC = Regs.NewSuperClass;
if (!SuperRegRC) {
assert(Regs.SrcOps.size() == 1);
Register SrcReg = MI.getOperand(Regs.SrcOps.front().OpIdx).getReg();
SuperRegRC = MRI.getRegClass(SrcReg);
}
auto CopyOrRegSeq = MRI.createVirtualRegister(SuperRegRC);

// Rewrite register defs to use CopyOrRegSeq, and replace all register
// operands using the old register (now dead).
for (const OperandSubRegMapping &DstOp : Regs.DstOps) {
auto DstReg = MI.getOperand(DstOp.OpIdx).getReg();
LLVM_DEBUG(llvm::dbgs()
<< "Rewriting tied pair: Dst=" << MI.getOperand(DstOp.OpIdx)
<< " Src=" << MI.getOperand(Regs.SrcOp.OpIdx) << "\n");
<< "Rewriting tied pair: Dst=" << MI.getOperand(DstOp.OpIdx));
// MI should be in SSA form and fully define its destination registers.
// Existing subregs make rewriting operands harder.
assert(!MI.getOperand(DstOp.OpIdx).getSubReg());
replaceRegOperands(DstReg, CopyReg, DstOp.SubRegIdx, MRI);
replaceRegOperands(DstReg, CopyOrRegSeq, DstOp.SubRegIdx, MRI);
LLVM_DEBUG(llvm::dbgs() << " to " << MI.getOperand(DstOp.OpIdx) << "\n");
}

// In case of a single SrcOp, insert a copy before MI from SrcReg to
// CopyOrRegSeq. This is breaking SSA, as CopyOrRegSeq is re-defined by MI. In
// case of multiple SrcOps, create a REG_SEQUENCE with the subregisters.
if (Regs.SrcOps.size() == 1 && !Regs.SrcOps.front().SubRegIdx) {
auto SrcReg = MI.getOperand(Regs.SrcOps.front().OpIdx).getReg();
BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII.get(TargetOpcode::COPY))
.addReg(CopyOrRegSeq, RegState::Define)
.addReg(SrcReg);
} else {
auto MIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
TII.get(TargetOpcode::REG_SEQUENCE), CopyOrRegSeq);
for (const OperandSubRegMapping &SrcOp : Regs.SrcOps) {
Register SrcReg = MI.getOperand(SrcOp.OpIdx).getReg();
const unsigned SrcSubRegIdx = MI.getOperand(SrcOp.OpIdx).getSubReg();
MIB.addReg(SrcReg,
MI.getOperand(SrcOp.OpIdx).isUndef() ? RegState::Undef : 0,
SrcSubRegIdx);
MIB.addImm(SrcOp.SubRegIdx);
}
LLVM_DEBUG(llvm::dbgs() << "Inserted: " << *MIB.getInstr());
}

// Rewrite register sources to use CopyOrRegSeq.
for (const OperandSubRegMapping &SrcOp : Regs.SrcOps) {
LLVM_DEBUG(llvm::dbgs()
<< "Rewriting tied pair: Src=" << MI.getOperand(SrcOp.OpIdx));
MI.getOperand(SrcOp.OpIdx).setReg(CopyOrRegSeq);
MI.getOperand(SrcOp.OpIdx).setSubReg(SrcOp.SubRegIdx);
MI.getOperand(SrcOp.OpIdx).setIsKill(false);
LLVM_DEBUG(llvm::dbgs() << " to " << MI.getOperand(SrcOp.OpIdx) << "\n");
}
MI.getOperand(Regs.SrcOp.OpIdx).setReg(CopyReg);
MI.getOperand(Regs.SrcOp.OpIdx).setIsKill(false);

// Insert a copy before MI from SrcReg to CopyReg. This is breaking SSA, as
// CopyReg is re-defined by MI.
BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(TargetOpcode::COPY))
.addReg(CopyReg, RegState::Define)
.addReg(SrcReg);
}

} // end anonymous namespace
Expand Down
9 changes: 6 additions & 3 deletions llvm/lib/Target/AIE/AIETiedRegOperands.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -4,18 +4,21 @@
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
// (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
// (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
//
//===----------------------------------------------------------------------===//

#include "AIETiedRegOperands.h"
#include <cassert>

using namespace llvm;

const OperandSubRegMapping *
TiedRegOperands::findOperandInfo(unsigned OpIdx) const {
if (SrcOp.OpIdx == OpIdx)
return &SrcOp;
assert(SrcOps.size() == 1 && "Expected only one SrcOp (NoSubRegister) ");

if (SrcOps.front().OpIdx == OpIdx)
return &SrcOps.front();
for (const OperandSubRegMapping &DstOp : DstOps) {
if (DstOp.OpIdx == OpIdx)
return &DstOp;
Expand Down
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