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Pull requests: Xilinx/llvm-aie

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Pull requests list

[AIE2P] Instruction select G_SELECT.
#291 opened Jan 20, 2025 by SagarMaheshwari99 Loading…
3
[AIE2P] Select 1024-bit and 512-bit load/store in the FIFO register bank
#290 opened Jan 20, 2025 by khallouh Loading…
[AIE2P] Add support for a new FIFO Register Bank
#288 opened Jan 20, 2025 by khallouh Loading…
[AIE2P] Support CopyPhysReg of L and EXP registers
#287 opened Jan 20, 2025 by khallouh Loading…
1
[AIE2P] Extend AIESubRegConstrainer for FIFO ops
#286 opened Jan 20, 2025 by andcarminati Loading…
10
[AIE2P] Combine G_SHUFFLE_VECTOR into Extract+Broadcast
#284 opened Jan 20, 2025 by katerynamuts Loading…
8
[AIE2P] Enable legalization of 4x128-bit G_CONCAT_VECTORS
#283 opened Jan 17, 2025 by konstantinschwarz Loading…
3
[AIE2P] Legalize G_UNMERGE_VALUES 256-bit vector to 2 128-bit vectors
#282 opened Jan 17, 2025 by niwinanto Loading…
7
[AIE2P] Add missing mac/mul frontend intrinsics
#281 opened Jan 17, 2025 by abnikant Loading…
5
[AIE2P] Implemented VST.PACK combine
#280 opened Jan 17, 2025 by katerynamuts Loading…
17
End to end support for bfp16 mac/mul intrinsics
#279 opened Jan 17, 2025 by niwinanto Loading…
4
End to end support for bfp16 scl2vec intrinsics
#278 opened Jan 17, 2025 by niwinanto Loading…
15
[AMD] avoid using upstream ci container
#276 opened Jan 17, 2025 by stephenneuendorffer Loading…
[AIE2P] Legalization and instruction selection support for G_FADD/G_FSUB
#274 opened Jan 16, 2025 by katerynamuts Loading…
3
[AIE] Legalize G_AND for <8 x s64> vector.
#262 opened Jan 15, 2025 by SagarMaheshwari99 Loading…
1
Combine vextract and vbroadcast into VEXTBCST
#257 opened Jan 13, 2025 by abhinay-anubola Loading…
3
[AIE] Solve it. Work In Progress adding a solver-based postpipeliner
#255 opened Jan 10, 2025 by martien-de-jong • Draft
[AIE NFC] Postpipeliner cleanups and refactorings
#253 opened Jan 8, 2025 by martien-de-jong Loading…
9
[AIEX] Schedule SWP epilogue with "free" instructions
#247 opened Dec 10, 2024 by andcarminati Loading…
141
Rename GPR Register in innermost loop body
#245 opened Nov 26, 2024 by F-Stuckmann • Draft
27
Add support for bfloat in VInsert PreLegalizerCombiner
#243 opened Nov 21, 2024 by abhinay-anubola Loading…
23
[AIE2] Fix memory access cycle for TM instructions
#240 opened Nov 20, 2024 by katerynamuts • Draft
5
Support for allowing direct VEXTRACT to 20-bit registers
#233 opened Nov 8, 2024 by abhinay-anubola Loading…
61
[AIEX] Ignore bank conflict if in the next cycle we cannot schedule the instruction.
#229 opened Nov 1, 2024 by krishnamtibrewala • Draft
11
[GlobalISel] Match G_SHUFFLE_VECTORs representing sub-vector extracts
#224 opened Oct 25, 2024 by konstantinschwarz • Draft
14
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