[AIE2P] Legalize G_UNMERGE_VALUES 256-bit vector to 2 128-bit vectors #282
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niwinanto
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abnikant,
andcarminati,
gbossu,
khallouh,
konstantinschwarz,
martien-de-jong,
SagarMaheshwari99 and
stephenneuendorffer
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| @@ -551,8 +551,10 @@ AIE2PLegalizerInfo::AIE2PLegalizerInfo(const AIE2PSubtarget &ST) | |||
| const LLT &DstTy = Query.Types[0]; | |||
| const LLT &SrcTy = Query.Types[1]; | |||
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| return SrcTy.isVector() && DstTy.isScalar() && | |||
| DstTy == SrcTy.getElementType(); | |||
| return (DstTy.isVector() && SrcTy.getSizeInBits() == 256 && | |||
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Could you add a comment to explain which cases this handles? (for both the existing and new case)
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| @@ -231,6 +231,57 @@ bool AIELegalizerHelper::legalizeG_BUILD_VECTOR(LegalizerHelper &Helper, | |||
| return true; | |||
| } | |||
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Can we have a description of the input->output of this custom legalization rule?
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| // Concatenate the src1 and src2 vectors, shift right | ||
| // and extract the resulting lower 512-bit vector | ||
| def G_AIE_VSHIFT : AIEGenericInstruction { |
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I was expecting "right" to be visible in the opcode itself. If I see this opcode there is no way to discover that it does right shift without looking to the comment.
| const AIEBaseInstrInfo *II = ST.getInstrInfo(); | ||
| const unsigned UnpadOpc = II->getGenericUnpadVectorOpcode(); | ||
| const Register SrcReg = MI.getOperand(MI.getNumOperands() - 1).getReg(); | ||
| const Register Dst1Reg = MI.getOperand(0).getReg(); |
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nit: maybe DstRegLow and DstRegHigh to improve readability.
| MIRBuilder.buildInstr(TargetOpcode::G_IMPLICIT_DEF, {SrcTy}, {}) | ||
| .getReg(0); | ||
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| const LLT Vec512 = |
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nit: const LLT Vec512 = SrcTy.multiplyElements(2);
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| // VSHIFT operates on 512-bit inputs. We need to pad the 256-bit source | ||
| // operand to 512-bit | ||
| const Register ImplicitDef256 = |
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nit: const Register ImplicitDef256 = MIRBuilder.buildUndef(SrcTy).getReg(0);
| MIRBuilder.buildConcatVectors({Vec512}, {SrcReg, ImplicitDef256}); | ||
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| // The second input will be ignored. Just create a dummy input | ||
| auto ImplicitDef512 = |
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nit: auto ImplicitDef512 = MIRBuilder.buildUndef(Vec512);
This PR introduces
G_AIE_VSHIFTgMIR opcode which is selected tovshiftinstruction. And this is utilized to legalize G_UNMERGE_VALUES 256-bit vector to 2 128-bit vector.