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[Deps] Add "pyyaml==6.0.1" dependency to Dockerfile #6

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Jan 21, 2025
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1 change: 1 addition & 0 deletions docker/Dockerfile.finn
Original file line number Diff line number Diff line change
Expand Up @@ -118,6 +118,7 @@ RUN pip install pytest-metadata==1.7.0
RUN pip install pytest-html==3.0.0
RUN pip install pytest-html-merger==0.0.8
RUN pip install pytest-cov==4.1.0
RUN pip install pyyaml==6.0.1

# extra dependencies from other FINN deps
# installed in Docker image to make entrypoint script go faster
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11 changes: 5 additions & 6 deletions src/finn/builder/build_dataflow_config.py
Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,7 @@
from typing import Any, List, Optional

from finn.transformation.fpgadataflow.vitis_build import VitisOptStrategy
from finn.util.basic import alveo_default_platform, alveo_part_map, pynq_part_map
from finn.util.basic import alveo_default_platform, part_map


class AutoFIFOSizingMethod(str, Enum):
Expand Down Expand Up @@ -370,11 +370,10 @@ def _resolve_driver_platform(self):
def _resolve_fpga_part(self):
if self.fpga_part is None:
# lookup from part map if not specified
if self.shell_flow_type == ShellFlowType.VIVADO_ZYNQ:
return pynq_part_map[self.board]
elif self.shell_flow_type == ShellFlowType.VITIS_ALVEO:
return alveo_part_map[self.board]
else:
try:
fpga_part = part_map[self.board]
return fpga_part
except KeyError:
raise Exception("Couldn't resolve fpga_part for " + self.board)
else:
# return as-is when explicitly specified
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1 change: 1 addition & 0 deletions src/finn/util/basic.py
Original file line number Diff line number Diff line change
Expand Up @@ -81,6 +81,7 @@
part_map = {**pynq_part_map, **alveo_part_map}
part_map["VEK280"] = "xcve2802-vsvh1760-2MP-e-S"
part_map["VCK190"] = "xcvc1902-vsva2197-2MP-e-S"
part_map["V80"] = "xcv80-lsva4737-2MHP-e-s"


def get_rtlsim_trace_depth():
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1 change: 0 additions & 1 deletion tests/fpgadataflow/test_fifosizing.py
Original file line number Diff line number Diff line change
Expand Up @@ -70,7 +70,6 @@ def test_fifosizing_linear(method, topology):
synth_clk_period_ns=10.0,
board="Pynq-Z1",
rtlsim_batch_size=100 if topology == "tfc" else 2,
shell_flow_type=build_cfg.ShellFlowType.VIVADO_ZYNQ,
generate_outputs=[
build_cfg.DataflowOutputType.ESTIMATE_REPORTS,
build_cfg.DataflowOutputType.STITCHED_IP,
Expand Down