Firtool Release 1.37.0

What's Changed

• [ExportVerilog] Remove unused output port wires by @uenoku in #4868
• [FIRRTL] prune duplicate conditions from mux trees by @darthscsi in #4872
• Beginning bump, fixed some tests by @azidar in #4845
• [FIRRTL] Narrow And, Or, and Xor by @darthscsi in #4875
• [FIRRTL] Merge constants in concatinations and drop double inversion by @darthscsi in #4876
• [FIRRTL] Add canonicalizers for subaccesses on invalid values by @fabianschuiki in #4866
• [FIRRTL][InferWidths] Infer InvalidValueOp to zero width by default by @fabianschuiki in #4863
• Fix InnerSymDCE, add support for erasing+setting inner symbols by @dtzSiFive in #4787
• [FIRRTL][ModuleInliner] Update anno's on mod's, update ports 1x. by @dtzSiFive in #4880
• [CalyxToHW] Support multiple guarded assigns to the same destination by @xerpi in #4890
• [PyCDE] Start of proper documentation by @teqdruid in #4888
• [Arc] Add state lowering pass by @fabianschuiki in #4729
• [OM] Add support for Class definitions and Fields. by @mikeurbach in #4837
• Enhance Upload Firtool Binaries by @jackkoenig in #4887
• LLVM bump to latest master by @adkian-sifive in #4881
• [ModuleInliner] Rework instance rename code, fix issue as w/PR4882. by @dtzSiFive in #4894
• [FIRRTLToHW] Simplify lowerRegConnect, support HW wires by @fabianschuiki in #4826
• [FIRRTLToHW] Lower FIRRTL wires to HW wires by @fabianschuiki in #4827
• [FIRRTLToHW] Create most temporary wires as hw.wire by @fabianschuiki in #4828
• [ESI] Data window model by @teqdruid in #4864
• [HWArithToHW] Make operation conversion fully generic by @mortbopet in #4898
• Upload full sources with release by @GeorgeLyon in #4901
• [Arc] Add state allocation passes by @fabianschuiki in #4730
• [Seq] Fix compat w/GCC12 (see #4900). by @dtzSiFive in #4902
• [Arc] Add basic LLVM lowering by @fabianschuiki in #4685
• [Arc] Add arc resets/enables, mux-to-control-flow pass, and ZeroCount op by @fabianschuiki in #4686
• [FIRRTL] Add parsing support for reference types + operations currently supported. by @dtzSiFive in #4858
• [FIRRTL] RefSendOp: support non-passive input, return ref-of-passive by @dtzSiFive in #4801
• [Arc] LowerState: support enable and reset operands by @maerhart in #4806
• [Arc] Add pure CallOp by @maerhart in #4809
• [FIRRTLUtils] Add more getBaseType helpers to reduce boilerplate. by @dtzSiFive in #4904
• [FIRRTL] Don't reject probes of non-passive. by @dtzSiFive in #4905

Full Changelog: firtool-1.36.0...firtool-1.37.0

Firtool Release 1.36.0

What's Changed

• [FIRRTL] RefConnect for references by @darthscsi in #4798
• [PyCDE] Include capnp, kj libs in wheel by @teqdruid in #4799
• [Arc] Add deduplication pass by @fabianschuiki in #4698
• [Arc] Add module force-inlining pass by @fabianschuiki in #4699
• [Arc] Add arcilator convenience tool by @fabianschuiki in #4700
• [FIRRTL][InferWidths] Honor upper bounds on AttachOp by @fabianschuiki in #4796
• [PyCDE] Package collateral SV and binaries by @teqdruid in #4808
• Bump LLVM by @azidar in #4805
• [ExportVerilog] Avoid splitting wire decl and assign in expr inlining by @fabianschuiki in #4819
• [firtool] Remove many unsued CL options by @youngar in #4820
• [HW] Allow inlining of all constant and aggregate ops. by @jopperm in #4506
• [Support] Add ImplicitSSAName directive for string attributes by @fabianschuiki in #4821
• [HW] Add hw.wire operation by @fabianschuiki in #4822
• [ExportVerilog] Add hw.wire emission support by @fabianschuiki in #4823
• [FIRRTLToHW] Lower FIRRTL node to HW wire by @fabianschuiki in #4824
• [Arc] Add loop splitting pass by @fabianschuiki in #4714
• [Arc] Add constant sinking pass by @fabianschuiki in #4715
• [Arc] Add lookup table generation pass by @fabianschuiki in #4682
• [Arc] Add makeshift input preprocessing by @fabianschuiki in #4683
• [Arc] Add variadic op simplification pass by @fabianschuiki in #4724
• [Arc] Add pass to remove unused arc arguments by @fabianschuiki in #4725
• [Arc] Add lookup table op and lowering pass by @fabianschuiki in #4726
• [Arc] Add simple arc inlining pass by @fabianschuiki in #4727
• [Arc] Add Comb to MLIR Arith conversion pass by @fabianschuiki in #4728
• [FIRRTL] F{Ext,Int}Module: build with parameters, internalPaths. by @dtzSiFive in #4829
• [Arc] Add tap op to observe ports/wires and AddTaps pass by @fabianschuiki in #4684
• [SCFToCalyx] Read "calyx.port_name" Attribute from FuncOp arguments/results by @xerpi in #4841
• [FIRRTL][CheckCombLoops] Improve loop reporting diagnostics. by @dtzSiFive in #4847
• [HWMemSimSimpl] Add rw_addr_collision = yes to memories with registered read addresses by @nandor in #4852
• [IMCP] Make field sensitive by @uenoku in #4795
• [Arc] Remove unobservable StateOps by @maerhart in #4810
• [reduce] Fix crash on nested ops; fix poor scaling of module op counting by @fabianschuiki in #4860
• [OM] Initial implementation of the OM dialect. by @mikeurbach in #4836
• Do not use non-const lvalue-refs with enumerate by @albertchen-sifive in #4855
• [Arc] SplitLoops: process splits in dependency order by @maerhart in #4865
• [Docs] Add recommended LoweringOptions by target by @uenoku in #4854
• [FIRParser] Don't try to parse LPKEYWORD as primitive. by @dtzSiFive in #4861
• [ExportVerilog] Add lowering option to not emit version comment by @rsetaluri in #4811
• [FIRRLT] Narrow adds by @darthscsi in #4869

New Contributors

• @xerpi made their first contribution in #4841

Full Changelog: firtool-1.35.0...firtool-1.36.0

SiFive Internal Release 1.5.5

What's Changed

• Backport "[ExtractInstances] Fix nondeterminism with MapVector. (#4749)" to sifive 1.5 by @uenoku in #4833

Full Changelog: sifive/1/5/4...sifive/1/5/5

SiFive Internal Release 1.22.5

What's Changed

• Backport "[ExtractInstances] Fix nondeterminism with MapVector. (#4749)" to SiFive 1.22 by @uenoku in #4832

Full Changelog: sifive/1/22/4...sifive/1/22/5

Firtool Release 1.35.0

What's Changed

• [FIRRTL] Canonicalizers: simplify resolve-of-send and hoist ref.sub out of ref.send. by @dtzSiFive in #4764
• [LowerSeqToSV] Use a dynamic index for array registers if possible by @uenoku in #4689
• [FIRRTL][LowerXMR] Fix XMR to instance port/result. by @dtzSiFive in #4767
• [Support] Move JSON-to-Attribute conversion to Support by @nandor in #4769
• [HWToLLVM] Remove unnecessary target materializations by @maerhart in #4761
• [Support][NFC] Factor out ImplicitSSAName directive by @fabianschuiki in #4774
• [FIRRTL] Fix Mem Metadata DUT/No-DUT Logic by @seldridge in #4768
• [FIRRTL] Fix MemToRegOfVec DUT/No DUT Behavior by @seldridge in #4775
• [FIRRTL][NFCI] Cleanup some casting/types, leverage TypedValue a bit. by @dtzSiFive in #4778
• [ExportVerilog] Fix crash in isDuplicatableExpression by @uenoku in #4782
• [FIRRTL] MemToRegOfVec: Fix threading issue, performance improvement. by @dtzSiFive in #4779
• [FIRRTL] Remove Buildable from FIRRTL hardware types by @trilorez in #4742
• [FIRRTL] Support 'module' as identifier for instance names by @adkian-sifive in #4589
• [FIRRTL] make IMCP correct for registers and more aggressive by @darthscsi in #4777
• [FIRRTL][NFC] Convert isDuplexValue to iterative instead of recursive. by @dtzSiFive in #4784
• [FIRRTL] Refactor errors emitted during return type inference. by @dtzSiFive in #4783
• [RegisterOpt] Add implicit ext/trunc by @uenoku in #4788
• [FIRRTL][NFC] FModuleLike: fixup method descriptions to match what they do. by @dtzSiFive in #4792
• [HW][NFC] InnerSymbolOpInterface: fixup method descriptions to match what they do. by @dtzSiFive in #4793
• [HW][InnerSym] Add InnerSymbolOpInterface::setInnerSymbolAttr by @dtzSiFive in #4790
• [HW] Add InnerSymAttr::erase. by @dtzSiFive in #4791

Full Changelog: firtool-1.34.0...firtool-1.35.0

Firtool Release 1.34.0

What's Changed

• Remove pipelining from simplified single-address memory reads by @nandor in #4739
• [ExportVerilog] Remove comments for instances emitted as binds by @rwy7 in #4732
• [Arc] Verify that arc bodies are pure by @maerhart in #4750
• Bump LLVM by @dtzSiFive in #4754
• [LLHD] Only permit signal creation in entity and proc ops by @maerhart in #4757
• [HWToLLVM] Add support for aggregate constant op by @maerhart in #4756
• [FIRRTL] Correct memory lowering behaviour for vb-to-bv conversion by @rwy7 in #4746
• [ESI][XRT] Start of MMIO: magic number and version by @teqdruid in #4759
• [FIRRTLFolds] Fix width mismatch by @uenoku in #4762
• [FIRRTL][NFCI] Use FConnectLike to abstract over connection types. by @dtzSiFive in #4765
• [FIRRTL][LowerXMR] Don't crash if encounter unexpected ref.sub. by @dtzSiFive in #4763

Full Changelog: firtool-1.33.0...firtool-1.34.0

Firtool Release 1.33.0

EDIT: firtool 1.33.0 has a known issue in canonicalizers which causes a complication failure so please use firtool 1.34.0.

What's Changed

• [Arc] Add arc conversion pass by @fabianschuiki in #4697
• [FIRRTLFolds] Add a mux canonicalize pattern by @prithayan in #4720
• [ESI] Option to flatten struct messages by @teqdruid in #4712
• [PyCDE] Set dialect attributes on modules, expose flatten dialect attr by @teqdruid in #4723
• [ExportVerilog] More support for SV attributes by @uenoku in #4716
• LLVM bump by @dtzSiFive in #4704
• [FIRRTL][NFCI] Move RefType to ODS by @dtzSiFive in #4731
• Disable folder for 4734 by @darthscsi in #4735
• [Support] Move FirtoolPassInstrumentation to a support header, NFC by @uenoku in #4738
• [ExportVerilog] Lowering option to emit 'wire' in port list by @teqdruid in #4737
• [ESI] Add more flexibility to port names during lowering by @teqdruid in #4736
• [FIRRTL] Instrinsic Modules by @darthscsi in #4733
• [FIRRTL] Add a pass to convert VoB -> BoV conversion by @rwy7 in #4654
• [SV] Move emitAsComment to SVAttributeAttr; remove SVAttributesAttr by @fabianschuiki in #4743
• [ExportVerilog] Add KEEP attr to Vivado array index bug workaround by @fabianschuiki in #4744
• [CI] Swap build mode of gcc and clang by @uenoku in #4747
• [ExtractInstances] Fix nondeterminism by using MapVector. by @uenoku in #4749

Full Changelog: firtool-1.32.0...firtool-1.33.0

Firtool Release 1.32.0

Overview

• Implement an iterative Tarjan's SCC to detect cycles
• Fix insertion point for fieldID.
• Bump LLVM to top-of-tree
• Add a canonicalization to swap constant index and unknown index of array gets
• Tweak suggested release tags, suggest firtool over sifive.
• Handle all data-flow ops in FieldSource
• Make DUT module public
• Limit BitCast to passive output, fix non-passive input.
• Handle port dontTouch, add inner sym.
• Replace single-address memories with registers
• Propapate bin flags through icmp and variadic op canonicalizer
• Disable one folder for 25% end-to-end perf improvement.
• Fixups to avoid memory safety issues.
• Reduce dontTouch+zero-width error to warning.
• Improve MacOS published binaries and flow
• Allow wiring type-equivalent types.
• Add disallowArrayIndexInlining option
• Unshallow CIRCT clone in uploadBinaries workflow
• Use port locations for diagnostics, don't dump module.
• Add a workflow for building and uploading Python wheels.

What's Changed

• [CheckCombCycles] Implement an iterative Tarjan's SCC to detect cycles by @prithayan in #4642
• [ESI] Introduce pure_module.input and pure_module.output by @teqdruid in #4657
• [ESI] Lower pure modules into HW modules by @teqdruid in #4658
• [FIRRTL][LegacyWiring] Fix insertion point for fieldID. by @dtzSiFive in #4664
• Bump LLVM to top-of-tree by @seldridge in #4666
• [HW] Add a canonicalization to swap constant index and unknown index of array gets by @uenoku in #4668
• [cmake] Tweak suggested release tags, suggest firtool over sifive. by @dtzSiFive in #4676
• Handle all data-flow ops in FieldSource by @darthscsi in #4673
• silence warning by @darthscsi in #4678
• [LowerAnnotations] Make DUT module public by @uenoku in #4672
• Fix Combinational Component Builder by @andrewb1999 in #4680
• [FIRRTL] Limit BitCast to passive output, fix non-passive input. by @dtzSiFive in #4648
• [LowerToHW] Handle port dontTouch, add inner sym. by @dtzSiFive in #4675
• [MemOp] Replace single-address memories with registers by @nandor in #4687
• [ESI] [mostly NFC] Lower ports pass refactoring by @teqdruid in #4670
• [ESI] Initial FIFO signaling: read latency 0 style by @teqdruid in #4679
• [CombFolds] Propapate bin flags through icmp and variadic op canonicalizer by @uenoku in #4695
• [Arc] Add dialect by @fabianschuiki in #4681
• [Handshake] Fix incorrect operation deletion in EliminateCBranchIntoMux canonicalization pattern by @RamirezLucas in #4650
• [COMB] disable one folder for 25% end-to-end perf improvement. by @darthscsi in #4690
• [FIRRTL][FoldMemRegs] Fixups to avoid memory safety issues. by @dtzSiFive in #4702
• [LowerToHW] Reduce dontTouch+zero-width error to warning. by @dtzSiFive in #4703
• Improve MacOS published binaries and flow by @jackkoenig in #4701
• [LowerAnnotations] Allow wiring type-equivalent types. by @dtzSiFive in #4656
• [ExportVerilog] Add disallowArrayIndexInlining option by @fabianschuiki in #4706
• Unshallow CIRCT clone in uploadBinaries workflow by @jackkoenig in #4707
• [LowerToHW] Use port locations for diagnostics, don't dump module. by @dtzSiFive in #4708
• [PyCDE] Expose signaling and FIFO0 by @teqdruid in #4705
• [CI] Add a workflow for building and uploading Python wheels. by @mikeurbach in #4710
• [ESI] Add parameters to PureModule lowering by @teqdruid in #4711

Full Changelog: firtool-1.31.0...firtool-1.32.0

Firtool Release 1.31.0

What's Changed

• Bump llvm to 78056e2f2d9510d2ace42fe7e9eb60e5abe8a3e7 by @rwy7 in #4645
• [FIRRTL][MemOp] Removed unused bits from memories by @nandor in #4652
• [LowerTypes] Track public modules and force lowering properly by @uenoku in #4655
• [ESI] Add specification to build signals into SV interface or not by @teqdruid in #4653

Full Changelog: firtool-1.30.0...firtool-1.31.0

Firtool Release 1.30.0

What's Changed

• [Pipeline] Plumb values through the pipeline + Support multi-cycle Ops by @matth2k in #4414
• [PyCDE] Class based struct definitions by @teqdruid in #4607
• [PyCDE][NFC] Cleanups and renames by @teqdruid in #4610
• [FIRRTL][GC] Always generate the scope yaml file by @youngar in #4612
• [HW][MSFT] Fix creating modules with InOut typed ports by @youngar in #4583
• Bump LLVM to 95e49f5a74c9e79778a62cc58b15875613cf9e59. by @mikeurbach in #4609
• [PyCDE] Improve type string representations by @teqdruid in #4616
• [PyCDE][NFC] Create signals from Python objects through Types by @teqdruid in #4611
• [LowerToHW] Lower aggregate constant by @uenoku in #4608
• Add port location information to verilog output by @youngar in #4540
• Migrate to the new folding api by @rwy7 in #4619
• [LLVM] Bump for CVE-2022-24439 by @teqdruid in #4621
• [CHIRRTL][NFC] Indicate using new fold API to squelch warnings. by @dtzSiFive in #4627
• [GC] Update numXMRs statistic. by @dtzSiFive in #4628
• [HW][NFC] InnerRef: Remove unused method definition by @dtzSiFive in #4629
• [ExportVerilog][PrettifyVerilog] Fix exprInEventControl by @uenoku in #4625
• [FIRRTL][NFC] Remove unused port boring/LCA methods. by @dtzSiFive in #4630
• [firtool] Use CIRCT's StripDebInfo pass instead of upstream by @youngar in #4632
• [FIRRTL] Remove extra whitespace around optional attr dicts by @rwy7 in #4324
• [ESI] Baseline XRT support by @teqdruid in #4537
• [FIRRTL] Support Chisel loadMemoryFromFile and loadMemoryFromFileInline by @seldridge in #4622
• [LowerAnnotations] Resolve legacy wiring annotations as WiringProblems by @sam-shahrestani in #4496
• [HWLegalizeModules] Legalize aggregate constant by @uenoku in #4626
• [ESI] Introduce ESI pure module op by @teqdruid in #4633
• [PyCDE] ESI pure module entry by @teqdruid in #4635
• [ESI][Cosim Runner] Add support for running binaries by @teqdruid in #4639
• [SV][ETC] Name port after instance result name, as well. by @dtzSiFive in #4640
• [firtool][NFC] Test relative path searching for includes. by @dtzSiFive in #4641
• [FIRRTL][AddSeqMemPorts] Fix use of DenseMap entry after invalidated. by @dtzSiFive in #4643
• [FIRRTL] Simple points-to like analysis by @darthscsi in #4637

New Contributors

• @sam-shahrestani made their first contribution in #4496

Full Changelog: firtool-1.29.0...firtool-1.30.0