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[AIE2P] Extend AIESubRegConstrainer for FIFO ops #286
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Covering also *InstrInfo required changes.
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$qex2, $p1, $lf1, $r25, $dc1, $dc4 = VLDB_POP_704_3D $plfr1, $d0_3d, implicit-def $srfifo_uf | ||
$qex2, $p1, $lf1, $r25, $dc2, $dc4 = VLDB_POP_704_3D $plfr1, $d0_3d, implicit-def $srfifo_uf | ||
$qex2, $p1, $lf1, $r25, $dc3, $dc6 = VLDB_POP_704_3D $plfr1, $d0_3d, implicit-def $srfifo_uf | ||
$x6, $p1, $lf1, $r25, $dc1, $dc5 = VLDB_POP_512_3D $p0, $lf0, $r24, $d1_3d, implicit-def $srfifo_uf |
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@@ -94,6 +99,8 @@ bool AIE2PPassConfig::addRegAssignAndRewriteOptimized() { | |||
if (AllocateMRegsFirst) | |||
addPass(createGreedyRegisterAllocator(onlyAllocateMRegisters)); | |||
if (EnableStagedRA) { | |||
addPass(createGreedyRegisterAllocator(onlyAllocatePLFRRegisters)); | |||
addPass(createAIESuperRegRewriter()); |
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Could you extend staged-ra-rewrite.mir
with a few cases for PLFR registers?
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Also, it would be nice to have an end-to-end test that showcases the benefit of StagedRA for PLFR registers like we have one for 2D and 3D addressing registers? Maybe a reduced example from Conv2D?
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See llvm/test/CodeGen/AIE/aie2p/addr_1d2d3d.ll
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name: test_composed_subreg |
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We have the same test in tie-subregs-pass-vld.mir
. I suppose this is related to that other outdated comment. Maybe you should rebase?
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They were actually moved/refactored, they are not duplicated.
%3:edc = COPY $r3 | ||
%4:ep = COPY $p0 | ||
%10:ed = REG_SEQUENCE %4, %subreg.sub_mod, %1, %subreg.sub_dim_size, %2, %subreg.sub_dim_stride, %3, %subreg.sub_dim_count | ||
$x11, %471:eps, %21:eldfiforeg, %22:erf2, %474:edc = VLDA_POP_512_2D %100, %101, %102, %10, implicit-def $srfifo_uf |
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We have the same tests in tie-subregs-pass-vld.mir
. Could you update those instead or remove them?
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They were actually moved/refactored, they are not duplicated.
Covering also *InstrInfo required changes. Also includes some test refactoring.
Based on the original work from @gbossu and @khallouh.